![background image](http://html.mh-extra.com/html/yaskawa/vipa-system-slio/vipa-system-slio_manual_907132279.webp)
Here is valid:
n
Rising edge: Edge 0-1
n
Falling edge: Edge 1-0
n
The input delay can be configured per channel in groups of 4.
n
An input delay of 0.1ms is only possible with "fast" inputs, which have a max. input
. Within a group, the input delay for
slow inputs is limited to 0.5ms.
n
Range of values: 0.1ms / 0.5ms / 3ms / 15ms
12.6.4
Digital output
12.6.4.1
Overview
n
12xDC 24V, 0.5A
n
Sub module
‘DI16/DO12’
n
Chap. 5.5 ‘Digital output’ page 126
12.6.4.2
Parametrization in SPEED7 Studio
12.6.4.2.1
‘I/O addresses’
Sub module
Output address
Access
Assignment
DI16/DO12
136
BYTE
Digital output Q+0.0 ... Q+0.7 (X5)
137
BYTE
Digital output Q+1.0 ... Q+1.3 (X5)
12.6.5
Counter
12.6.5.1
Overview
n
4 channels
n
Sub module:
‘Counter’
n
12.6.5.2
Parametrization in SPEED7 Studio
12.6.5.2.1
‘I/O addresses’
Sub module
Input address
Access
Assignment
Count
816
DINT
Channel 0: Counter value / Frequency value
820
DINT
Channel 1: Counter value / Frequency value
824
DINT
Channel 2: Counter value / Frequency value
828
DINT
Channel 3: Counter value / Frequency value
Input delay
VIPA System SLIO
Configuration with VIPA SPEED7 Studio
Deployment I/O periphery > Counter
HB300 | CPU | 013-CCF0R00 | en | 19-30
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