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Hardware interrupt
Description
Assignment
Hardware gate opening
Hardware interrupt by edge 0-1 exclusively at HW gate
channel 3
n
enabled: Process interrupt by edge 0-1 exclusively at
HW gate channel 3 with open SW gate
n
disabled: no hardware interrupt
disabled
Hardware gate closing
Hardware interrupt by edge 1-0 exclusively at HW gate
channel 3
n
enabled: Process interrupt by edge 1-0 exclusively at
HW gate channel 3 with open SW gate
n
disabled: no hardware interrupt
disabled
On reaching comparator
Hardware interrupt on reaching
comparator
n
enabled: Hardware interrupt when comparator is trig-
gered, can be configured via
‘Characteristics of the
output’
n
disabled: no hardware interrupt
disabled
Overflow
Hardware interrupt overflow
n
enabled: Hardware interrupt on overflow the upper
counter limit
n
disabled: no hardware interrupt
disabled
Underflow
Hardware interrupt on underrun
n
enabled: Hardware interrupt on underflow the lower
counter limit
n
disabled: no hardware interrupt
disabled
Max. frequency
Description
Assignment
Counting signals/HW gate
Specify the max. frequency for track A/pulse,
track B/direction and HW gate
60kHz
Frequency
shortest permissible count pulse
1kHz
400
µ
s
2kHz
200
µ
s
5kHz
80
µ
s
10kHz
40
µ
s
30kHz
13
µ
s
60kHz
6.7
µ
s
Latch
Specify the max. frequency for the latch signal
10kHz
Frequency
shortest permissible latch pulse
1kHz
400
µ
s
2kHz
200
µ
s
5kHz
80
µ
s
10kHz
40
µ
s
30kHz
13
µ
s
60kHz
6.7
µ
s
VIPA System SLIO
Deployment I/O periphery
Counting > Parametrization
HB300 | CPU | 013-CCF0R00 | en | 19-30
134