W83627DHG
Publication Release Date: Aug, 22, 2007
-21- Version
1.4
5.11.6 GPIO-5 Interface
SYMBOL PIN I/O
DESCRIPTION
GP50 I/O
12t
General-purpose I/O port 5 bit 0. (Default after strapping)
EN_GTL IN
cu
During VSB power reset (RSMRST), this pin is pulled high
internally and is defined as VID transition voltage level (GTL or
TTL), and the value is shown at CR2C bit 3. The PCB layout
should reserve space for a 1-k
Ω
resistor to pull down this pin if
TTL is the selected VID level.
WDTO#
77
O
12
Watchdog Timer output signal.
GP51 I/OD
12t
General-purpose I/O port 5 bit 1.
RSMRST#
75
OD
12
Resume reset signal output.
GP52 I/OD
12t
General-purpose I/O port 5 bit 2.
SUSB#
73
IN
t
System S3 state input.
GP53 I/OD
12t
General-purpose I/O port 5 bit 3.
PSON#
72
OD
12
Power supply on-off output.
GP54 I/OD
12t
General-purpose I/O port 5 bit 4.
PWROK
71
OD
12
This pin generates the PWROK signal while 3VCC comes in.
GP55 I/O
12t
General-purpose I/O port 5 bit 5. (Default)
EN_ACPI IN
cd
During VSB power reset (RSMRST), this pin is pulled down
internally and is defined as EN_ACPI (enabling particular ACPI
functions), which provides the value for CR2C bit 4 (EN_ACPI).
The PCB layout should reserve space for a 1-k
Ω
resistor to pull
down this pin to ensure successful disabling of particular ACPI
functions, and a 1-k
Ω
resistor is recommended to pull the pin up if
wish to enable particular ACPI functions. (This pin function is both
for UBE and UBF version only)
SUSLED
70
O
12
Suspended LED output.
GP56
I/OD
12t
General-purpose I/O port 5 bit 6.
PSIN#
68
IN
tu
Panel Switch Input.
This pin is active-low with an internal pulled-up
resistor.
GP57 I/OD
12t
General-purpose I/O port 5 bit 7.
PSOUT#
67
OD
12
Panel Switch Output. This signal is used to wake-up the system
from S3/S5
state.
5.11.7 GPIO-6 Interface
See 5.4 Serial Port & Infrared Port Interface
Summary of Contents for W83627DHG
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