W83627DHG
Publication Release Date: Aug, 22, 2007
-124- Version
1.4
10.2 Register Descriptions
There are several status, data, and control registers in the W83627DHG. These registers are defined
below, and the rest of this section provides more details about each one of them.
ADDRESS REGISTER
OFFSET READ
WRITE
base a 0
base a 1
base a 2
base a 3
SA REGISTER
SB REGISTER
TD REGISTER
DO REGISTER
TD REGISTER
base a 4
MS REGISTER
DR REGISTER
base a 5
DT (FIFO) REGISTER
DT (FIFO) REGISTER
base a 7
DI REGISTER
CC REGISTER
10.2.1 Status Register A (SA Register) (Read base a 0)
Along with the SB register, the SA register is used to monitor several disk-interface pins in PS/2 and
Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
1
2
3
4
5
6
7
0
WP#
INDEX#
HEAD
TRAK0#
STEP
DRV2#
INIT PENDING
DIR
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
RESERVED (Bit 6)
STEP (Bit 5):
This bit indicates the complement of the STEP# output.
TRAK0#(Bit 4):
This bit indicates the value of the TRAK0# input.
HEAD (Bit 3):
This bit indicates the complement of the HEAD# output.
0 side
0
1 side
1
Summary of Contents for W83627DHG
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