W83627DHG
Publication Release Date: Aug, 22, 2007
-205- Version
1.4
CR E4h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
R / W
Disable / Enable to issue a 4s long PSOUT# low pulse when the system
returns from power loss state and is supposed to be “off” as described in
CRE4[6:5], Logical Device A.
(
VBAT
)
0: Disable.
1: Enable.
6~5
R / W
Power-loss control bits => (
VBAT
)
00: System always turns off when it returns from power-loss state.
01: System always turns on when it returns from power-loss state.
10: System turns off / on when it returns from power-loss state depending
on the state before the power loss.
11: User defines the state before power loss.(i.e. the last state set of
CRE6[4])
4
R / W
VSBGATE# Enable bit =>
0: Disable.
1: Enable.
* This bit is available both for UBE and UBF version
3
R / W
Keyboard wake-up options.
(LRESET#)
0: Password or sequence hot keys programmed in the registers.
1: Any key.
2
R / W
Enable the hunting mode for all wake-up events set in CRE0. This bit is
cleared when any wake-up events is captured.
(LRESET#)
0: Disable.
1: Enable.
1~0 Reserved.
CR E5h. (GPIOs Reset Source Register; Default 00))
BIT
READ / WRITE
DESCRIPTION
7~ 5 Reserved.
4
R / W
VID_MRST
0: VID reset by LRESET#.
1: VID reset by PWROK.
3
R / W
GP23_MRST
0: GP23 reset by LRESET#.
1: GP23 reset by PWROK.
2
R / W
GP22_MRST
0: GP22 reset by LRESET#.
1: GP22 reset by PWROK.
Summary of Contents for W83627DHG
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