W83627DHG
Publication Release Date: Aug, 22, 2007
-184- Version
1.4
CR 2Ah. (SPI Configuration; Default 00h) (VSB Power)
BIT
READ / WRITE
DESCRIPTION
7~6
R / W
Serial Peripheral Interface Configuration bit.
(VSB) – These two bits are
for UBE and UBF version only
= 00 Normal read. SPI clock is 16MHz.
= 01 Normal read. SPI clock is 33MHz.
= 10 Normal read. SPI clock is 22MHz.
= 11 Reserved.
Note: These two bits are ignored when CR24, bit 1 is “0” (SPI function
is disabled).
5~4
R / W
Serial Peripheral Interface configuration bit.
(VBAT)
= 00 Normal read. The clock rate is based on the setting of CR[2Ah],
bits[7:6]
= 01 Reserved
= 10 Reserved
= 11 Fast read with one dummy byte. The clock rate is 33MHz.
If set to “11”, CR[2Ah], bits[7:6] must be 0.
Note: These two bits are ignored when CR24, bit 1 is “0”. (SPI function is
disabled)
3 R/W
SDA_filter_EN:
0: Enable SDA input to a filter
1: Disable SDA input to a filter
2
R / W
SCL_filter_EN:
0: Enable SCL input to a filter
1: Disable SCL input to a filter
1
R / W
Pin 89, Pin 90 function select (I
2
C interface)
= 0 {Pin 89, Pin 90}
Æ
set by CR2C bits[6:5].
= 1 {Pin 89, Pin 90}
Æ
SDA, SCL.
0
R / W
KB, MS pin function select
= 0 KB, MS function.
= 1 GPIO function.(GP24, GP25, GP26 and GP27)
* Normal Read: Read 1-byte data.
Fast Read: Read 4-byte data.
CR 2Bh. (Reserved)
Summary of Contents for W83627DHG
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