W83627DHG
Publication Release Date: Aug, 22, 2007
-162- Version
1.4
13.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is
controlled by LD5-CRF0 as follows:
13.5.1 KB Control Register
BIT
7 6 5 4 3 2 1 0
NAME
KCLKS1 KCLKS0 Reserved Reserved Reserved
P92EN HGA20 HKBRST
KCLKS1, KCLKS0
These two bits select the KBC clock rate.
00: KBC clock input is 6 MHz
01: KBC clock input is 8 MHz
10: KBC clock input is 12 MHz
11: KBC clock input is 16 MHz
P92EN
(Port 92 Enable)
1: Enables Port 92 to control GATEA20 and KBRESET.
0: Disables Port 92 functions.
HGA20
(Hardware GATEA20)
1: Selects hardware GATEA20 control logic to control GATE A20 signal.
0: Disables hardware GATEA20 control logic function.
HKBRST
(Hardware Keyboard Reset)
1: Selects hardware KB RESET control logic to control KBRESET signal.
0: Disables hardware KB RESET control logic function.
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATEA20 according to received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the
KBRESET is pulse low for 6
μ
s (Min.) with a 14
μ
s (Min.) delay.
GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually
exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set.
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