W83627DHG
Publication Release Date: Aug, 22, 2007
-135- Version
1.4
In the PS/2 Model 30 mode, the bit definitions are as follows:
1
2
3
4
5
6
7
0
DRATE0
DRATE1
NOPREC
X
X
X
X
X
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit disables the precompensation function. It can be set by the software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base a 4)) for how the settings correspond to individual data rates.
Summary of Contents for W83627DHG
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