W83627DHG
Publication Release Date: Aug, 22, 2007
-248- Version
1.4
21.3.10.13.
ECP Parallel Port Reverse Timing
t2
t1
t3
t4
t5
t5
t6
PD<0:7>
nACK
nAUTOFD
21.3.11 KBC Timing Parameters
SYMBOL DESCRIPTION MIN.
MAX.
UNIT
T1
Address Setup Time from WRB
0
nS
T2
Address Setup Time from RDB
0
nS
T3 WRB
Strobe
Width
20
nS
T4
RDB Strobe Width
20
nS
T5
Address Hold Time from WRB
0
nS
T6
Address Hold Time from RDB
0
nS
T7
Data Setup Time
50
nS
T8
Data Hold Time
0
nS
T9
Gate Delay Time from WRB
10
30
nS
T10
RDB to Drive Data Delay
40
nS
T11
RDB to Floating Data Delay
0
20
nS
T12
Data Valid After Clock Falling (SEND)
4
μ
S
T13
K/B Clock Period
20
μ
S
T14
K/B Clock Pulse Width
10
μ
S
T15
Data Valid Before Clock Falling (RECEIVE)
4
μ
S
T16
K/B ACK After Finish Receiving
20
μ
S
T19 Transmit
Timeout
2
mS
T20
Data Valid Hold Time
0
μ
S
T21
Input Clock Period (6
−
16 Mhz)
63 167 nS
Summary of Contents for W83627DHG
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