W83627DHG
Publication Release Date: Aug, 22, 2007
-14- Version
1.4
5.5 KBC
Interface
SYMBOL PIN I/O
DESCRIPTION
GA20M 59 O
12
Gate A20 output. This pin is high after system reset. (KBC P21)
KBRST 60 O
12
Keyboard reset. This pin is high after system reset. (KBC P20)
KCLK I/OD
16ts
Keyboard
Clock.
GP27
62
I/OD
16t
General-purpose I/O port 2 bit 7.
KDAT I/OD
16ts
Keyboard
Data.
GP26
63
I/OD
16t
General-purpose I/O port 2 bit 6.
MCLK I/OD
16ts
PS2
Mouse
Clock.
GP25
65
I/OD
16t
General-purpose I/O port 2 bit 5.
MDAT I/OD
16ts
PS2
Mouse
Data.
GP24
66
I/OD
16t
General-purpose I/O port 2 bit 4.
5.6 Serial Peripheral Interface
The SPI employs a master-slave model and typically has three signal lines: serial data input line (SI),
serial data output line (SO), and serial clock line (SCK). Different slaves are addressed on the bus by
chip select signals from the master. The data bits are first shifted in/out the most significant bit (MSB).
The data are often shifted simultaneously out from the output pin and into the input pin. Among the
parameters, only the communication lines and the clock edge are defined by the SPI. The others differ
from device to device.
SPI Operation
To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This
synchronizes the slave device with the W83627DHG. Data can now be transferred between the
W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the
falling edge of the clock.
In a slave device, a logic low is received on the SCE# line and the clock input is at the SCK pin, which
synchronizes the slave with the W83627DHG. Data is then received serially at the SI pin. During a write
cycle, data is shifted out to the SO pin on clocks from the W83627DHG.
Summary of Contents for W83627DHG
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