W83627DHG
Publication Release Date: Aug, 22, 2007
-197- Version
1.4
CR F6h. (WDTO# Counter Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~0
R / W
Watch Dog Timer Time-out value. Writing a non-zero value to this
register causes the counter to load the value into the Watch Dog
Counter and start counting down. If CR F7h, bits 7 and 6 are set,
any Mouse Interrupt or Keyboard Interrupt event causes the
previously-loaded, non-zero value to be reloaded to the Watch Dog
Counter and the count down resumes. Reading this register returns
the current value in the Watch Dog Counter, not the Watch Dog Timer
Time-out value.
00h: Time-out Disable
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 second/minutes
03h: Time-out occurs after 3 second/minutes
……………………….......................................
FFh: Time-out occurs after 255 second/minutes
CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
R / W
Mouse interrupt reset enables watch-dog timer reload
0: Watchdog timer is not affected by mouse interrupt.
1: Watchdog timer is reset by mouse interrupt.
6
R / W
Keyboard interrupt reset enables watch-dog timer reload
0: Watchdog timer is not affected by keyboard interrupt.
1: Watchdog timer is reset by keyboard interrupt.
5
Write “1” Only Trigger WDTO# event. This bit is self-clearing.
4
R / W
Write “0” Clear
WDTO# status bit
0: Watchdog timer is running.
1: Watchdog timer issues time-out event.
3~0
R / W
These bits select the IRQ resource for the WDTO#. (02h for SMI# event.)
Summary of Contents for W83627DHG
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