W83627DHG
Publication Release Date: Aug, 22, 2007
-168- Version
1.4
Three control bits (ENMDAT_UP, MSRKEY, MSXKEY) define the combinations of the mouse wake-up
events. Please see the following table for the details.
Table 14.1
ENMDAT_UP
(LOGICAL DEVICE A,
CR[E6H], BIT 7)
MSRKEY
(LOGICAL DEVICE A,
CR[E0H], BIT 4)
MSXKEY
(LOGICAL
DEVICE A,
CR[E0H], BIT 1)
WAKE-UP EVENT
1 x
1
Any button clicked or any
movement.
1 x
0
One click of the left or right
button.
0
0
1
One click of the left button.
0
1
1
One click of the right button.
0
0
0
Two clicks of the left button.
0
1
0
Two clicks of the right button.
14.3 Resume Reset Logic
The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the
South Bridge.
When the W83627DHG detects the 3VSB voltage rises to “V1”, it then starts a delay – “t1” before the
rising edge of RSMRST# asserting. If the 3VSB voltage falls below “V2”, the RSMRST# de-asserts
immediately.
Timing and voltage parameters are shown in Figure 14.5 and Table 14.2.
t1
V1
RSMRST#
3VSB
V2
Figure 14.5
Summary of Contents for W83627DHG
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