W83627DHG
Publication Release Date: Aug, 22, 2007
-20- Version
1.4
5.11.4 GPIO-3 Interface
SYMBOL PIN I/O
DESCRIPTION
RSTOUT0# 94 OD
12
PCI Reset Buffer 0.
RSTOUT1# 93 O
12
PCI Reset Buffer 1.
GP30 I/OD
12t
General-purpose I/O port 3 bit 0.
PWROK2
92
OD
12
This pin generates the PWROK2 signal while 3VCC comes in.
(This pin function is both for UBE and UBF version only)
GP31 I/OD
12t
General-purpose I/O port 3 bit 1.
VSBGATE#
91
O
12
Switch 3VSB power to memory when in S3 state. The default is
disabled while the particular ACPI functions are enabled. The
control bit is at Logical Device A, CR[E4h] bit 4.(This pin function
is both for UBE and UBF version only)
GP32 I/OD
12t
General-purpose I/O port 3 bit 2.
RSTOUT2# O
12
PCI Reset Buffer 2. (Default)
SCL
90
IN
ts
Serial
Bus
clock.
GP33 I/OD
12t
General-purpose I/O port 3 bit 3.
RSTOUT3# O
12
PCI Reset Buffer 3. (Default)
SDA
89
I/OD
12ts
Serial bus bi-directional Data.
GP34 I/OD
12t
General-purpose I/O port 3 bit 4.
RSTOUT4#
88
O
12
PCI Reset Buffer 4. (Default)
GP35 I/OD
12t
General-purpose I/O port 3 bit 5.
ATXPGD
87
IN
t
ATX power good input signal. It is connected to the PWROK
signal from the power supply for PWROK/PWROK2 generation.
The default is enabled.(This pin function is both for UBE and UBF
version only)
GP36 I/OD
12t
General-purpose I/O port 3 bit 6.
FTPRST#
69
IN
t
Connect to the reset button. This pin has internal de-bounce
circuit whose de-bounce time is at least 32 mS. (This pin function
is both for UBE and UBF version only)
GP37 I/OD
12t
General-purpose I/O port 3 bit 7.
SUSC#
64
IN
t
SLP_S5# input. (This pin function is both for UBE and UBF
version only)
5.11.5 GPIO-4 Interface
See 5.4 Serial Port & Infrared Port Interface
Summary of Contents for W83627DHG
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