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Winbond W83627DHG, Manual

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Winbond W83627DHG Manual Download Page 226

W83627DHG 

 

Publication Release Date: Aug, 22, 2007 

-214- Version 

1.4 

Continued  

BIT 

READ / WRITE 

DESCRIPTION 

3~2 Reserved 

1 

R / W 

Return High Temperature 
0: The temperature of each agent is returned from domain 0 or domain 1, 
which is controlled by CRE0 bit 0~3. 
1: Return the highest temperature in domain 0 and domain 1 of individual 
Agent. 

0 

R / W 

PECISB_EN: 
0: PECI host is controlled by IO 
1: PECI host is the other (i.e. South Bridge). 

 

CR E8h. (PECI Warning Flag Register; Default 00h) 

BIT 

READ / WRITE 

DESCRIPTION 

7 

R / W 

Agent 4 Absent / Alert Bit 
0: Agent 4 is detected and has valid FCS 
1: Agent 4 cannot be detected or has invalid FCS in the previous 3 
transactions 

6 

R / W 

Agent 3 Absent / Alert Bit 
0: Agent 3 is detected and has valid FCS 
1: Agent 3 cannot be detected or has invalid FCS in the previous 3 
transactions 

5 

R / W 

Agent 2 Absent / Alert Bit 
0: Agent 2 is detected and has valid FCS 
1: Agent 2 cannot be detected or has invalid FCS in the previous 3 
transactions 

4 

R / W 

Agent 1 Absent / Alert Bit 
0: Agent 1 is detected and has valid FCS 
1: Agent 1 cannot be detected or has invalid FCS in the previous 3 
transactions 

3~2 Reserved. 

1~0 R/W 

PECI speed selected 
00: The PECI speed is 1.5 MHz 
01: The PECI speed is 750 KHz 
10: The PECI speed is 375 KHz 
11: The PECI speed is 187.5 KHz 

 

Summary of Contents for W83627DHG

Page 1: ...www DataSheet4U com www DataSheet4U com W83627DHG WINBOND LPC I O Note This document is for UBC UBE and UBF version except specified descriptions Date April 10 2007 Version 1 4 W83627DHG PCB 24...

Page 2: ......

Page 3: ...ections of SYSFANOUT and CPUFANOUT0 output type at CR 24h 5 Remove the description of the internal pulled up resistor of Parallel Port 6 Modify the definitions of edge level and enable disable debounc...

Page 4: ...at Hardware Monitor Device Bank 0 Index 57h bit6 9 Remove status bit of PME status of MIDI IRQ event at Logical Device A CRF4 bit 1 10 Remove control bit of enable disable PME of MIDI at Logical Devic...

Page 5: ...ing in Table 14 4 and section 21 3 3 12 N A 03 28 2007 1 3 N A 1 Add a new DC spec of RSMRST PWROK for UBF version In section 14 3 and 14 4 2 Add LPC Timing in section 21 4 3 Remove redundant Power on...

Page 6: ...Source 18 5 11 3 GPIO 2 Interface 19 5 11 4 GPIO 3 Interface 20 5 11 5 GPIO 4 Interface 20 5 11 6 GPIO 5 Interface 21 5 11 7 GPIO 6 Interface 21 5 11 8 GPIO 4 with WDTO SUSLED Multi function 22 5 12...

Page 7: ...ed Register Index 05h Bank 0 60 8 9 CPUTIN Target Temperature Register CPUFANIN0 Target Speed Register Index 06h Bank 0 61 8 10 Tolerance of Target Temperature or Target Speed Register Index 07h Bank...

Page 8: ...inbond Vendor ID Register Index 4Fh Bank 0 81 8 46 Reserved Register Index 50h 55h Bank 0 82 8 47 BEEP Control Register 1 Index 56h Bank 0 82 8 48 BEEP Control Register 2 Index 57h Bank 0 83 8 49 Chip...

Page 9: ...ex 53h Bank 2 99 8 81 AUXTIN Temperature Sensor Hysteresis Low Byte Register Index 54h Bank 2 99 8 82 AUXTIN Temperature Sensor Over temperature High Byte Register Index 55h Bank 2 100 8 83 AUXTIN Tem...

Page 10: ...ntrol Register HCR Read Write 140 11 2 4 Handshake Status Register HSR Read Write 140 11 2 5 UART FIFO Control Register UFR Write only 141 11 2 6 Interrupt Status Register ISR Read only 142 11 2 7 Int...

Page 11: ...wer Failure Resume 166 14 2 Wake Up the System by Keyboard and Mouse 167 14 2 1 Waken up by Keyboard events 167 14 2 2 Waken up by Mouse events 167 14 3 Resume Reset Logic 168 14 4 PWROK Generation 16...

Page 12: ...Absolute Maximum Ratings 216 21 2 DC CHARACTERISTICS 216 21 3 AC CHARACTERISTICS 225 21 3 1 AC Power Failure Resume Timing 225 21 3 2 VSBGATE Timing for UBE and UBF Version Only 230 21 3 3 Clock Input...

Page 13: ...ts UARTs one of which provides IR functions IrDA 1 0 SIR for 1 152K bps Each UART includes a 16 byte send receive FIFO a programmable baud rate generator complete modem control capability and a proces...

Page 14: ...he read electronics yFDD anti virus functions with software write protect and FDD write enable signal write data signal forced to be inactive ySupport 3 5 inch or 5 25 inch floppy disk drives yCompati...

Page 15: ...MART FAN TM I Thermal CruiseTM and Speed CruiseTM modes and SMART FAN TM III yProgrammable threshold temperature to speed fan fully while current temperature exceeds this threshold in the Thermal Crui...

Page 16: ...tinguish whether the input pins undergo any transitions by reading the registers All of the 3 GPIOs can assert PSOUT or PME to wake up the system if each of them undergoes any transition OnNow Functio...

Page 17: ...ace signals Printer port interface signals ACPI General purpose I O pins Hardware Monitor channel and Vref KBC Keyboard Mouse data and clock HM W83627DHG UARTA interface signals UARTB interface signal...

Page 18: ...8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 AVCC 3VSB 3VSB 3VCC 3VCC 3VCC VTT VBAT GP37 KDAT GP26 KCLK GP27 3VSB KBRST GA20M SI AUXFANIN1 RIA GP60 DCDA GP61 VSS SOU...

Page 19: ...CPUD PECISB Vtt PECI NC NC AUXFANIN0 CPUFANIN0 SYSFANIN SST CPUFANOUT0 SYSFANOUT FAN_SET PLED BEEP SO GP21 CPUFANIN1 GP20 CPUFANOUT1 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 DRVDEN0 GP23 SCK INDEX MOA...

Page 20: ...rectional pin Open drain output with 12 mA sink capability I OD12t TTL level bi directional pin Open drain output with 12 mA sink capability I OD12cs CMOS level bi directional Schmitt trigger pin Open...

Page 21: ...input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole This input pin needs to connect a pulled up 1 K resistor to 5V for Floppy Driv...

Page 22: ...ter is selected See the description of the parallel port for the definition of this pin in ECP and EPP modes PE 32 INts PRINTER MODE An active high input on this pin indicates that the printer has det...

Page 23: ...12ts PRINTER MODE PD1 Parallel port data bus bit 1 See the description of the parallel port for the definitions of this pin in ECP and EPP modes PD2 40 I O12ts PRINTER MODE PD2 Parallel port data bus...

Page 24: ...RT A Data Terminal Ready An active low signal informs the modem or data set that the controller is ready to communicate PENROM INt During power on reset this pin is pulled down internally and is defin...

Page 25: ...tput GP42 83 I O12t General purpose I O port 4 bit 2 Note This pin changes to input state during internal PWROK from low to high then goes back to the previous setting state Please see the AP Note 1 o...

Page 26: ...nt slaves are addressed on the bus by chip select signals from the master The data bits are first shifted in out the most significant bit MSB The data are often shifted simultaneously out from the out...

Page 27: ...on for hardware monitor This pin is low after system reset SO 118 O8 Transfer commands address or data to serial flash This pin is connected to SI of serial flash CASEOPEN 76 INt CASE OPEN detection A...

Page 28: ...serial flash AUXFANIN0 111 CPUFANIN0 112 SYSFANIN 113 I O12ts 0 to 3 V amplitude fan tachometer input CPUFANIN1 I O12ts 0 to 3 V amplitude fan tachometer input Default GP21 119 I OD12t General purpos...

Page 29: ...3627DHG supports are the S0 working and S3 suspend to RAM states S0 is a full power state in which the computer is actively used S3 is a sleeping state in which the processor is powered down but the m...

Page 30: ...bi directional Data RSTOUT4 O12 PCI Reset Buffer 4 Default GP34 88 I OD12t General purpose I O port 3 bit 4 5 11 General Purpose I O Port 5 11 1 SMBus Interface SYMBOL PIN I O DESCRIPTION RSTOUT2 O12...

Page 31: ...ut Default GP22 I OD12t General purpose I O port 2 bit 2 SCE 19 O12 Serial flash ROM interface chip selection GP23 I OD12t General purpose I O port 2 bit 3 SCK 2 O12 Clock output for serial flash UBC...

Page 32: ...ult SCL 90 INts Serial Bus clock GP33 I OD12t General purpose I O port 3 bit 3 RSTOUT3 O12 PCI Reset Buffer 3 Default SDA 89 I OD12ts Serial bus bi directional Data GP34 I OD12t General purpose I O po...

Page 33: ...port 5 bit 4 PWROK 71 OD12 This pin generates the PWROK signal while 3VCC comes in GP55 I O12t General purpose I O port 5 bit 5 Default EN_ACPI INcd During VSB power reset RSMRST this pin is pulled d...

Page 34: ...wish to enable particular ACPI functions This pin function is both for UBE and UBF version only GP55 I O12t General purpose I O port 5 bit 5 SUSLED 70 O12 Suspended LED output VSBGATE O12 Switch 3VSB...

Page 35: ...VBAT 74 3 V on board battery for the digital circuits 3VCC 12 28 48 3 3 V power supply for driving 3 V on host interface AVCC 95 Analog 3 3 V power input Internally supply power to all analog circuit...

Page 36: ...Device A Hardware Monitor Logical Device B and PECI SST Logical Device C Each Logical Device has its own configuration registers above CR30 The host can access those registers by writing an appropria...

Page 37: ...t be followed in sequence 1 Enter the Extended Function Mode 2 Configure the configuration registers 3 Exit the Extended Function Mode 6 1 1 Enter the Extended Function Mode To place the chip into the...

Page 38: ...sumes that the EFER is located at 2Eh so the EFIR is located at 2Eh and the EFDR is located at 2Fh If the HEFRAS CR26 bit 6 is set 2Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh Enter the...

Page 39: ...B 22h R W FFh Device Power Down 23h R W 00h Immediate Power Down 24h R W 0100_0ss0b Global Option 25h R W 00h Interface Tri state Enable 26h R W 0s000000b Global Option 27h Reserved 28h R W 50h Global...

Page 40: ...nputs the W83627DHG can generate the following outputs Four PWM pulse width modulation or DC fan outputs for the fan speed control Beep tone output for warnings SMI OVT signals for system protection e...

Page 41: ...isters 59h 5Bh BANK 5 50h 5Ch Monitor Value Registers Fan Divisor Register II BANK 1 CPUTIN Temperature Control Status Registers 50h 56h BANK 2 AUXTIN Temperature Control Status Registers 50h 56h Seri...

Page 42: ...te 0 Start By Master 0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 627DHG R W Ack by 627DHG SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack by 784R Stop by Master SCL SDA Continued 7 8 0 7 8 0 7 8 Frame 2 Internal...

Page 43: ...e of the 8 bit ADC CPU Vcore voltage detection and temperature sensing 7 3 1 Voltages Over 2 048 V or Less Than 0 V Input voltages greater than 2 048 V should be reduced by external resistors to keep...

Page 44: ...n be set to 232 K and 10 K respectively to reduce negative input voltage V1 from 12 V to less than 2 048 V Both of these solutions are illustrated in the figure above 7 3 2 Voltage Detection The data...

Page 45: ...llustrated in the schematic below the thermistor is connected in series with a 10 K resistor and then connects to VREF pin 101 10K 1 RTHM VREF Pin 101 AUXTIN CPUTIN SYSTIN Pin 102 Pin 103 Pin 104 10K...

Page 46: ...rol lines In addition SST also includes variable data transfer rate established with every message Therefore it is comparatively flexible The W83627DHG has a programmable SST address defined at Logica...

Page 47: ...ent binary value It represents multiple of 1 64 C in the temperature reading Table 1 shows some typical temperature values in 16 bit two s complement format Table 1 Typical Temperature Values 16 BIT D...

Page 48: ...CR E8h bit 1 0 for PECI speed selection to meet the bit timing limits of CPU with PECI function We recommend this bit is set to 11 for better stability 2 Program Logical Device C CR E5h bit 7 4 for e...

Page 49: ...1h and AUXTIN Bank2 Index 50h 51h The source of the CPUTIN value is determined by the value programmed into the CPUFANOUT0 monitor Temperature source select register Hardware Monitor Device Bank 0 Ind...

Page 50: ...7 4 is designed for each PECI Agent to report whether the W83627DHG PECI host detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successi...

Page 51: ...equation RPM Count Divisor 135 106 The default divisor is 2 and is specified at Bank0 Index 47h bits 7 4 Index 4Bh bits 7 6 Index 4Ch bit 7 Index 59h bit 7 and bits 3 2 and Index 5Dh bits 5 7 There ar...

Page 52: ...at Bank0 Index 01h Index 03h Index 11h and Index 61h The duty cycle can be calculated using the following equation 100 255 Value Register bit 8 Programmed Dutycycle The default duty cycle is FFh or 10...

Page 53: ...SMART FAN TM I it is illustrated in the figure below 7 6 3 1 Thermal CruiseTM Mode Four pairs of temperature sensors and fan outputs in Thermal CruiseTM mode SYSTIN and SYSFANOUT CPUFANOUT0 and the t...

Page 54: ...still exceeds the high end a warning message is issued to protect the system 2 If the temperature falls below the high end i e 58 C but remains above the low end e g 52 C fan output remains the same...

Page 55: ...4Ah bits 7 5 Fan Speed CruiseTM mode keeps the fan speed in a specified range First this range is defined in BIOS by a fan speed count the amount of time between clock input signals not the number of...

Page 56: ...C Current SYS Temperature Bank 0 Index 27h SYSTIN Temperature Sensor Read only 8 MSB 1 C Current AUX Temperature Bank2 Index 50h 51h AUXTIN Temperature Sensor Read only 8 MSB 1 C bit 7 0 5 C Current C...

Page 57: ...ank0 14h Bit0 3 Bank0 16h Bank0 15h Bank0 12h Bit3 Bank0 17h CPUFANOUT1 Bank0 63h Bank0 62h Bit0 3 Bank0 65h Bank0 64h Bank0 12h Bit6 Bank0 66h Bank0 0Eh Bank0 0Fh Relative Registers at Fan Speed Crui...

Page 58: ...by Bank0 Index 49h bits 2 0 CPUFANOUT1 and the temperature sensor selected by Bank0 Index 4Ah bits 7 5 The algorithm is as follows 1 The target temperature temperature tolerance maximum and minimum f...

Page 59: ...ifts to Target Temperature Temperature Tolerance creating a new target temperature named Target Temperature 1 in this figure Min Fan Output Max Fan Output Fan output DC PWM Temperature Tolerance Tar C...

Page 60: ...ature falls lower than Target Temperature 1 Temperature Tolerance the fan speed is reduced one step again and the target temperature shifts to Target Temperature 1 Temperature Tolerance or Target Temp...

Page 61: ...utput Value Bank0 Index 03h CPUFANOUT0 Output Value Select 80h FFh by strapping bits 7 0 CPUFANOUT0 Value Current CPUFANOUT1 Output Value Bank0 Index 61h CPUFANOUT1 Output Value Select 80h FFh by stra...

Page 62: ...s a specified fan limit rises above it or falls below it This interrupt must be reset by reading all the interrupt status registers or subsequent events do not generate interrupts This mode is illustr...

Page 63: ...rature remains above TO until the temperature falls below THYST This interrupt must be reset by reading all the interrupt status registers or subsequent events do not generate interrupts This is illus...

Page 64: ...nabled by setting Bank0 Index 4Ch bit 6 to one In this mode the SMI pin can create an interrupt when the current temperature exceeds TO Over Temperature and continues to create interrupts until the te...

Page 65: ...interrupt modes comparator and interrupt The modes are illustrated in this figure T HYST Interrupt Reset when Temperature sensor registers are read OVT OVT Comparator Mode default Interrupt Mode To If...

Page 66: ...nsumption of the battery When the case is closed the signal of Pin 76 must be pulled high by an externally pulled up 2M resistor that is connected to Pin 74 Once the case is opened the signal will be...

Page 67: ...TIN exceeds the limit z Any fan input of the five pins SYSFANIN CPUFANIN0 AUXFANIN0 CPUFANIN1 and AUXFANIN1 exceeds the limit z CASEOPEN input pin is sampled low z User defined bit Bank 4 Index 53h bi...

Page 68: ...CR61 is 90h the Address Port is at 0x295h and the Data Port is at 0x296h 8 1 Address Port Port x5h Address Port Port 5h Power on Default Value 00h Attribute Bit 6 0 Read write Bit 7 Reserved Size 8 bi...

Page 69: ...ut Clock Source Select This bit selects the clock source for PWM output frequency 0 clock source is 24 MHz 1 clock source is 180 KHz Bit 6 0 SYSFANOUT PWM Pre Scale divider The clock source for PWM ou...

Page 70: ...5 CPUFANOUT0 PWM Output Frequency Configuration Register Index 02h Bank 0 Register Location 02h Power on Default Value 04h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 PWM_CLK_SEL2 PWM_SCALE2 The...

Page 71: ...to this eight bit value divided by 255 times 100 FFh creates a duty cycle of 100 and 00h creates a duty cycle of 0 2 If CPUFANOUT0 is programmed for DC Voltage output Bank0 Index 04h bit1 is 1 Bit 7 2...

Page 72: ...served and no function Bit 1 CPUFANOUT0 output mode selection 0 CPUFANOUT0 pin produces a PWM output duty cycle Default 1 CPUFANOUT0 pin produces DC output Bit 0 SYSFANOUT output mode selection 0 SYSF...

Page 73: ...an Speed CruiseTM mode Bit 7 0 CPUFANIN0 Target Speed 8 10 Tolerance of Target Temperature or Target Speed Register Index 07h Bank 0 Register Location 07h Power on Default Value 00h Attribute Read Wri...

Page 74: ...temperature keeps below low temperature limit then the fan speed keeps on decreasing until reaching a minimum value and this is Stop Value 8 12 CPUFANOUT0 Stop Value Register Index 09h Bank 0 Register...

Page 75: ...CruiseTM mode SYSFANOUT value increases from zero to this eight bit register value to provide a minimum value to turn on the fan 8 14 CPUFANOUT0 Start up Value Register Index 0Bh Bank 0 Register Loca...

Page 76: ...of 0 1 seconds The default time is 6 seconds 2 For DC output The units are intervals of 0 4 seconds The default time is 24 seconds 8 16 CPUFANOUT0 Stop Time Register Index 0Dh Bank 0 Register Locatio...

Page 77: ...vals of 0 1 seconds The default time is 1 seconds 2 For DC output The units are intervals of 0 4 seconds The default time is 4 seconds 8 18 Fan Output Step Up Time Register Index 0Fh Bank 0 Register L...

Page 78: ...ut Clock Source Select This bit selects the clock source of PWM output frequency 0 clock source is 24 MHz 1 clock source is 180 KHz Bit 6 0 AUXFANOUT PWM Pre Scale divider The clock source for PWM out...

Page 79: ...UT_MIN_Value CPUFANOUT0_MIN_Value SYSFANOUT_MIN_Value CPUFANOUT1_MIN_Value Reserved Bit 7 Reserved Bit 6 0 CPUFANOUT1 value decreases to zero when the temperature goes below the target range 1 CPUFANO...

Page 80: ...0 0 AUXFANOUT pin produces a PWM output duty cycle Default 1 AUXFANOUT pin produces DC output 8 22 AUXTIN Target Temperature Register AUXFANIN0 Target Speed Register Index 13h Bank 0 Register Location...

Page 81: ...ode Bit 3 0 Tolerance of AUXFANIN0 Target Speed 8 24 AUXFANOUT Stop Value Register Index 15h Bank 0 Register Location 15h Power on Default Value 01h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 AU...

Page 82: ...rovide a minimum value to turn on the fan 8 26 AUXFANOUT Stop Time Register Index 17h Bank 0 Register Location 17h Power on Default Value 3Ch Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 AUXFANOUT...

Page 83: ...temperature OVT output Bit 5 Reserved Bit 4 0 Compare mode Default 1 Interrupt mode Bit 3 0 Reserved 8 28 Reserved Registers Index 19h 1Fh Bank 0 8 29 Value RAM Index 20h 3Fh Bank 0 ADDRESS A6 A0 DESC...

Page 84: ...3 High Limit 38h VIN3 Low Limit 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit 3Bh SYSFANIN Fan Count Limit Note It is the number of counts of the internal clo...

Page 85: ...ill resume upon clearing of this bit Bit 2 Reserved Bit 1 A one enables the SMI Interrupt output Bit 0 A one enables startup of monitoring operations a zero puts the part in standby mode Note The outp...

Page 86: ...4 3 2 1 0 VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2 Bit 7 A one indicates that the CPUTIN temperature has been over the target temperature for three minutes at full fan speed in Thermal Cruis...

Page 87: ...rrupt See Interrupt Status Register 1 Index 41h Bank 0 8 34 SMI Mask Register 2 Index 44h Bank 0 Register Location 44h Power on Default Value FFh Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 VIN1...

Page 88: ...3 2 1 0 FANINC5 FANOPV5 FANINC4 FANOPV4 SYSFANIN DIV_B0 SYSFANIN DIV_B1 CPUFANIN0 DIV_B0 CPUFANIN0 DIV_B1 Bit 7 6 CPUFANIN0 Divisor bits1 0 See VBAT Monitor Control Register Index 5Dh Bank 0 Bit 5 4 S...

Page 89: ...7 1 8 39 CPUFANOUT0 AUXFANOUT monitor Temperature source select register Index 49h Bank 0 Register Location 49h Power on Default Value 00h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT0...

Page 90: ...re Source Select Register Index 4Ah Bank 0 Register Location 4Ah Power on Default Value 00h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved CPUFANOUT1 TEM...

Page 91: ...r Clock Input select 00 ADC clock select 22 5 KHz Default 01 ADC clock select 5 6 KHz 22 5K 4 10 ADC clock select 1 4 KHz 22 5K 16 11 ADC clock select 0 35 KHz 22 5K 64 Bit 3 2 Reserved These two bits...

Page 92: ...nk 0 Register Location 4Dh Power on Default Value 95h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved Bit 7 6 Reserved Bit 5 AUXFANIN...

Page 93: ...UXFANIN1_BP Reserved HBACS Bit 7 HBACS High byte access 1 Access Index 4Fh high byte register Default 0 Access Index 4Fh low byte register Bit 6 Reserved This bit should be set to zero Bit 5 BEEP outp...

Page 94: ...red value exceeds the threshold value 1 Enable BEEP output 0 Disable BEEP output Default Bit 6 BEEP output control for SYSFANIN if the monitored value exceeds the threshold value 1 Enable BEEP output...

Page 95: ...trol 1 Enable global BEEP output Default 0 Disable all BEEP output Bit 6 BEEP output control for VIN4 if the monitor value exceeds the limit value 1 Enable BEEP output 0 Disable BEEP output Default Bi...

Page 96: ...Default C1h 8 50 Diode Selection Register Index 59h Bank 0 Register Location 59h Power on Default Value 70h Attribute Read Write Size 8 bits CPUFANIN1 DIV_B0 CPUFANIN1 DIV_B1 SELPIIV1 SELPIIV2 SELPIIV...

Page 97: ...r Location 5Dh Power on Default Value 04h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved SYSFANIN DIV_B2 CPUFANIN0 DIV_B2 AUXFANIN0 DIV_B2 Bit 7 AUXFANIN...

Page 98: ...l temperature protection Default Bit 6 1 Enable AUXFANOUT critical temperature protection 0 Disable AUXFANOUT critical temperature protection Default Bit 5 1 Enable CPUFANOUT0 critical temperature pro...

Page 99: ...t Clock Source Select This bit selects the clock source for PWM output 0 clock source is 24 MHz 1 clock source is 180 KHz Bit 6 0 CPUFANOUT1 PWM Pre Scale divider The clock source of PWM output is div...

Page 100: ...nk 0 Register Location 62h Power on Default Value 40h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 Reserved CPUFANOUT1_SEL CPUFANOUT1_Mode CPUFANOUT1_Mode Target Temperature Tolerance CPUFANIN1 Ta...

Page 101: ...uiseTM mode Bit 7 0 CPUFANIN1 Target Speed 8 59 CPUFANOUT1 Stop Value Register Index 64h Bank 0 Register Location 64h Power on Default Value 01h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 CPUFAN...

Page 102: ...m value to turn on the fan 8 61 CPUFANOUT1 Stop Time Register Index 66h Bank 0 Register Location 66h Power on Default Value 3Ch Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Stop Time In...

Page 103: ...x Value In SMART FAN TM III mode the CPUFANOUT0 value increases to this value This value cannot be zero and it cannot be lower than the CPUFANOUT0 Stop value 8 63 CPUFANOUT0 Output Step Value Register...

Page 104: ...x Value In SMART FAN TM III mode the CPUFANOUT1 value increases to this value This value cannot be zero and it cannot be lower than the CPUFANOUT1 Stop value 8 65 CPUFANOUT1 Output Step Value Register...

Page 105: ...ull speed 8 67 CPUFANOUT0 Critical Temperature Register Index 6Ch Bank 0 Register Location 6Ch Power on Default Value FFh Attribute Read Write Size 8 bits In Thermal CruiseTM mode when the function of...

Page 106: ...Bank 0 Register Location 6Eh Power on Default Value FFh Attribute Read Write Size 8 bits In Thermal CruiseTM mode when the function of CPUFANOUT1 temperature sensing is enabled and the monitored tempe...

Page 107: ...6 5 4 3 2 1 0 TEMP 0 Reserved Bit 7 Temperature 0 of the CPUTIN sensor The nine bit value is in units of 0 5 C Bit 6 0 Reserved 8 72 CPUTIN Temperature Sensor Configuration Register Index 52h Bank 1 R...

Page 108: ...Register Location 53h Power on Default Value 4Bh Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 THYST 8 1 Bit 7 0 Hysteresis temperature bits 8 1 The nine bit value is in units of 0 5 C and the def...

Page 109: ...ize 8 bits 7 6 5 4 3 2 1 0 TOVF 8 1 Bit 7 0 Over temperature bits 8 1 The nine bit value is in units of 0 5 C and the default is 80 C 8 76 CPUTIN Temperature Sensor Over temperature Low Byte Register...

Page 110: ...sor The nine bit value is in units of 0 5 C 8 78 AUXTIN Temperature Sensor Temperature Low Byte Register Index 51h Bank 2 Register Location 51h Attribute Read Only Size 8 bits 7 6 5 4 3 2 1 0 TEMP 0 R...

Page 111: ...e select 0 Compared mode Default 1 Interrupt mode Bit 0 0 Monitor AUXTIN 1 Stop monitoring AUXTIN 8 80 AUXTIN Temperature Sensor Hysteresis High Byte Register Index 53h Bank 2 Register Location 53h Po...

Page 112: ...er temperature High Byte Register Index 55h Bank 2 Register Location 55h Power on Default Value 50h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 TOVF 8 1 Bit 7 0 Over temperature bits 8 1 The nine...

Page 113: ...3VSB VBAT TAR3 Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved Bit 7 6 Reserved Bit 5 A one indicates the fan count limit of AUXFANIN1 has been exceeded Bit 4 A one indicates the fan count limit of CPU...

Page 114: ...upt Status Register 3 Index 50h Bank 4 Bit 3 2 Reserved Bit 1 0 A one disables the corresponding interrupt status bit for the SMI interrupt See Interrupt Status Register 3 Index 50h Bank 4 8 86 Reserv...

Page 115: ...ower on Default Value 00h Attribute Read Write Size 8 bits 7 6 5 4 3 2 1 0 OFFSET 7 0 Bit 7 0 SYSTIN temperature offset value The value in this register is added to the monitored value so that the rea...

Page 116: ...d Register Index 57h 58h Bank 4 8 92 Real Time Hardware Status Register I Index 59h Bank 4 Register Location 59h Power on Default Value 00h Attribute Read Only Size 8 bits 7 6 5 4 3 2 1 0 CPUVCORE_STS...

Page 117: ...e is in the allowed range 8 93 Real Time Hardware Status Register II Index 5Ah Bank 4 Register Location 5Ah Power on Default Value 00h Attribute Read Only Size 8 bits 7 6 5 4 3 2 1 0 VIN1_STS TAR4_STS...

Page 118: ...re has not reached the warning range Bit 0 VIN1 Voltage status 1 VIN1 voltage is over or under the allowed range 0 VIN1 voltage is in the allowed range 8 94 Real Time Hardware Status Register III Inde...

Page 119: ...ange 0 3VSB voltage is in the allowed range 8 95 Reserved Register Index 5Ch 5Fh Bank 4 8 96 Value RAM 2 Index 50h 59h Bank 5 ADDRESS A6 A0 DESCRIPTION 50h 3VSB reading 51h VBAT reading The reading is...

Page 120: ...correct instructions and memory addresses to the SPI which responds with the corresponding data of the addresses The data are placed to the LPC bus by the Super I O W83627DHG and returned to the South...

Page 121: ...2 Data byte 2 Base 7 7 0 DATA3 Data byte 3 z Usages Write SPI instructions to Base 0 Set up the addresses and the data in Base 2 Base 7 Implement the instruction by setting the instruction mode in Bas...

Page 122: ...read FAST READ 4 bytes 8 CMD_Ad 3 _Da 1 _R Command with 3bytes address and 1byte data read READ Read Status Read ID ST SST 9 CMD_Ad 3 _Da 2 _R Command with 3bytes address and 2bytes data read Read ID...

Page 123: ...h the configure command The advantage of the FIFO is that it lets the system have a larger DMA latency without causing disk errors The following tables give several examples of the delays with the FIF...

Page 124: ...relative to the surrounding bits 10 1 4 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives Perpendicular recording differs from the...

Page 125: ...ead Number Select HLT Head Load Time HUT Head Unload Time LOCK Lock EFIFO FIFOTHR and PTRTRK bits to prevent being affected by software reset MFM MFM or FM Mode MT Multitrack N The number of data byte...

Page 126: ...W MT MFM SK 0 0 1 1 0 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system Resul...

Page 127: ...mand W MT MFM SK 0 1 1 0 0 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system R...

Page 128: ...d codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system FDD reads contents of all cylinder...

Page 129: ...ST1 ST2 Status information after command execution R R R R C H R N Disk status after the command has been completed 5 Verify PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W MT MFM SK 1 0 1 1 0 Com...

Page 130: ...ller 7 Write Data PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W MT MFM 0 0 0 1 0 1 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to Command execution W W R N W W EOT...

Page 131: ...and W MT MFM 0 0 1 0 0 1 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W W EOT GPL DTL Execution Data transfer between the FDD and the system...

Page 132: ...ector Sectors per Cylinder W W GPL D Gap 3 Filler Byte Execution for Each Sector Repeat W W W W C H R N Input Sector Parameters Result R R R ST0 ST1 ST2 Status information after command execution R R...

Page 133: ...D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 0 0 1 1 Command codes W W SRT HUT HLT ND 13 Seek PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 1 1 1 1 Command codes W W 0 0 0 0 0 HDS DS1...

Page 134: ...and W 0 0 0 0 1 1 1 0 Registers placed in FIFO Result R R R R R R R R R R PCN Drive 0 PCN Drive 1 PCN Drive 2 PCN Drive 3 SRT HUT HLT ND SC EOT LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL FIFOTHR PRETR...

Page 135: ...D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 0 1 0 0 Command Code W 0 0 0 0 0 HDS DS1 DS0 Result R ST3 Status information about the disk drive 20 Invalid PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS C...

Page 136: ...FIFO REGISTER DT FIFO REGISTER base address 7 DI REGISTER CC REGISTER 10 2 1 Status Register A SA Register Read base address 0 Along with the SB register the SA register is used to monitor several di...

Page 137: ...for this register are as follows 1 2 3 4 5 6 7 0 WP INDEX HEAD TRAK0 STEP F F DRQ INIT PENDING DIR INIT PENDING Bit 7 This bit indicates the value of the floppy disk interrupt output DRQ Bit 6 This b...

Page 138: ...e bit definitions for this register are as follows Drive SEL0 Bit 5 This bit indicates the status of the DO REGISTER bit 0 drive select bit 0 WDATA Toggle Bit 4 This bit changes state on every rising...

Page 139: ...pin which is latched on every rising edge of the WD output pin RDATA F F Bit 3 This bit indicates the complement of the latched RDATA output pin WE F F Bit 2 This bit indicates the complement of the...

Page 140: ...Register TD Register Read base address 3 This register is used to assign a particular drive number to the tape drive support mode of the data separator This register also holds the media ID drive type...

Page 141: ...B 1 FDD number 0 is in the SEEK mode Reserved FDC Busy CB A read or write command is in the process when CB HIGH Non DMA mode the FDC is in the non DMA mode this bit is set only during the execution p...

Page 142: ...lue of write precompensation The following tables show the precompensation values for every combination of these bits PRECOMP PRECOMPENSATION DELAY 2 1 0 250K 1 Mbps 2 Mbps Tape drive 0 0 0 Default De...

Page 143: ...at a time The FIFO register stores data commands and parameters and it provides disk drive status information In addition data bytes pass through the data register to program or obtain results after a...

Page 144: ...C tries to access a sector beyond the final sector of a cylinder 0 1 2 3 4 5 6 7 Status Register 2 ST2 1 2 3 4 5 6 7 0 BC Bad Cylinder MD Missing Address Mark in Data Field 1 If the FDC cannot find a...

Page 145: ...isk controller During a read of this register these bits are in tri stat DSKCHG In PS 2 mode the bit definitions are as follows 1 2 3 4 5 6 7 0 HIGH DENS DRATE0 DRATE1 DSKCHG 1 1 1 1 DSKCHG Bit 7 This...

Page 146: ...e of the FDC See DR register bits 1 and 0 Data Rate Register DR Register Write base address 4 for how the settings correspond to individual data rates 10 2 9 Configuration Control Register CC Register...

Page 147: ...X X X X X Reserved Bit 7 3 Reserved These bits should be set to 0 NOPREC Bit 2 This bit disables the precompensation function It can be set by the software DRATE1 DRATE0 Bit 1 0 These two bits select...

Page 148: ...it enable PBE Even parity enable EPE Parity bit fixed enable PBFE Set silence enable SSE Baudrate divisor latch access bit BDLAB Bit 7 BDLAB When this bit is set to logical 1 designers can access the...

Page 149: ...data length is 5 bits one and a half stop bits are sent and checked 3 If MSBE is set to logical 1 and the data length is 6 7 or 8 bits two stop bits are sent and checked Bits 0 and 1 DLS0 DLS1 These t...

Page 150: ...rol Register UCR Data Length Select Bit 0 DLS0 Data Length Select Bit 1 DLS1 Multiple Stop Bits Enable MSBE Parity Bit Enable PBE Even Parity Enable EPE Parity Bit Fixed Enable PBFE Set Silence Enable...

Page 151: ...s set to logical 1 when the transmit FIFO is empty It is set to logical 0 when the CPU writes data into TBR or the FIFO Bit 4 SBD This bit is set to logical 1 to indicate that received data are kept i...

Page 152: ...n diagnostic mode this bit is internally connected to the modem control input DCD Bit 2 This bit is only used in the diagnostic mode In diagnostic mode this bit is internally connected to the modem co...

Page 153: ...select Reserved Reserved RX interrupt active level LSB RX interrupt active level MSB Bit 6 7 These two bits are used to set the active level of the receiver FIFO interrupt The active level is the num...

Page 154: ...w Bit 0 This bit is logical 1 if there is no interrupt pending If one of the interrupt sources has occurred this bit is set to logical 0 ISR INTERRUPT SET AND FUNCTION Bit 3 Bit 2 Bit 1 Bit 0 Interrup...

Page 155: ...enable the RBR data ready interrupt 11 2 8 Programmable Baud Generator BLL BHL Read Write Two 8 bit registers BLL and BHL compose a programmable baud generator that uses 24 MHz to generate a 1 8461 MH...

Page 156: ...2400 19200 31200 48 3600 28800 46800 32 4800 38400 62400 24 7200 57600 93600 16 9600 76800 124800 12 19200 153600 249600 6 38400 307200 499200 3 57600 460800 748800 2 115200 921600 1497600 1 Unless sp...

Page 157: ...NUMBER OF W83627DHG PIN ATTRIBUTE SPP EPP ECP 1 36 O nSTB nWrite nSTB HostClk2 2 9 31 26 24 23 I O PD 0 7 PD 0 7 PD 0 7 10 22 I nACK Intr nACK PeriphClk2 11 21 I BUSY nWait BUSY PeriphAck2 12 19 I PE...

Page 158: ...s port R W 2 1 0 0 EPP data port 0 R W 2 1 0 1 EPP data port 1 R W 2 1 1 0 EPP data port 2 R W 2 1 1 1 EPP data port 2 R W 2 Notes 1 These registers are available in all modes 2 These registers are av...

Page 159: ...her Normally this signal is active for approximately 5 s before BUSY stops Bit 5 A logical 1 means the printer has detected the end of paper Bit 4 A logical 1 means the printer is selected Bit 3 A log...

Page 160: ...ata must be present for a minimum of 0 5 s before and after the strobe pulse 12 2 4 EPP Address Port The address port is available only in EPP mode Bit definitions are as follows 1 2 3 4 5 6 7 0 PD0 P...

Page 161: ...ad or write operation 12 2 7 EPP Operation When EPP mode is selected the PDx bus is in standard or bi directional mode when no EPP read write or address cycle is being executed In this situation all o...

Page 162: ...maximum bandwidth requirement The size of the FIFO is 16 bytes The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed The ECP port har...

Page 163: ...r A cnfgB Base 401h R W 111 Configuration Register B ecr Base 402h R W All Extended Control Register Note The base addresses are specified by CR60 and 61 which are determined by the configuration regi...

Page 164: ...s 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 ECP FIFO Address RLE A data byte written to this address is placed in the FIFO and tagged as an ECP Address RLE The hardware at the ECP port...

Page 165: ...ests from the parallel port to the CPU on the low to high transition on ACK Bit 3 This bit is inverted and output to the SLIN output 0 The printer is not selected 1 The printer is selected Bit 2 This...

Page 166: ...ng an 8 bit implementation 12 3 9 CNFGB Configuration Register B Mode 111 The bit definitions are as follows 7 6 5 4 3 2 1 0 1 1 1 intrValue compress IRQx 0 IRQx 1 IRQx 2 Bit 7 This bit is read only I...

Page 167: ...ode When the direction is 0 forward direction bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and automatically transmitted to the peripheral using the ECP...

Page 168: ...FO contains at least one byte of data 1 The FIFO is completely empty 12 3 11 ECP Pin Descriptions NAME TYPE DESCRIPTION NStrobe HostClk O This pin loads data or address into the slave on its asserting...

Page 169: ...signal to default to the deasserted state d Set mode 011 ECP Mode ECP address RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively 12 3 12 1 Mode Switchin...

Page 170: ...to or from the ecpDFifo tFifo or CFifo DMA uses the standard PC DMA services The ECP requests DMA transfers from the host by activating the PDRQ pin The DMA empties or fills the FIFO using the approp...

Page 171: ...22 P11 KIRQ MIRQ GATEA20 KBRST P17 KINH GP I O PINS P12 P16 KDAT KCLK MCLK MDAT Multiplex I O PINS Keyboard and Mouse Interface 13 1 Output Buffer The output buffer is an 8 bit read only register at I...

Page 172: ...em flag bit in the command byte of the keyboard controller It defaults to 0 after a power on reset 3 Command Data 0 Data byte 1 Command byte 4 Inhibit Switch 0 Keyboard is inhibited 1 Keyboard is not...

Page 173: ...f test succeeds ABh Interface Test BIT 04 03 02 01 00 BIT DEFINITION No Error Detected Keyboard Clock line is stuck low Keyboard Clock line is stuck high Keyboard Data line is stuck low Keyboard Data...

Page 174: ...92 functions HGA20 Hardware GATEA20 1 Selects hardware GATEA20 control logic to control GATE A20 signal 0 Disables hardware GATEA20 control logic function HKBRST Hardware Keyboard Reset 1 Selects har...

Page 175: ...0 Res 0 Res 1 Res 0 Res 0 Res 1 SGA20 PLKBRST SGA20 Special GATE A20 Control 1 Drives GATE A20 signal to high 0 Drives GATE A20 signal to low PLKBRST Pull Low KBRESET A logical 1 on this bit causes K...

Page 176: ...writing a 1 before enabling its corresponding bit in the PME interrupt registers 2 The PME interrupt registers of wake up event At Logical Device A CR F6h and CR F7h Each wake up event can be enabled...

Page 177: ...nal is held low for as long as the PSIN is held low The South Bridge controls the SUSB signal through the PSOUT signal The PSON is directly connected to the power supply to turn on or off the power Fi...

Page 178: ...power failure depending on the state before the power failure Please see Note 1 11 User defines the state before the power failure The previous state is set at CRE6 4 Please see Note 2 Note1 The W8362...

Page 179: ...s going to be read or written through CR E2h According to IBM 101 102 keyboard specification a complete key code contains a 1 byte make code and a 2 byte break code For example the make code of 0 is 0...

Page 180: ...f the left or right button 0 0 1 One click of the left button 0 1 1 One click of the right button 0 0 0 Two clicks of the left button 0 1 0 Two clicks of the right button 14 3 Resume Reset Logic The R...

Page 181: ...e of PWROK asserting If the 3VCC voltage falls below V4 the PWROK de asserts immediately Timing and voltage parameters are shown in Figure 14 6 and Table 14 3 t2 V3 V4 PWROK 3VCC Figure 14 6 SYMBOL PA...

Page 182: ...example if Logical Device A CR E6h bit 2 is set to 0 and bits 2 1 are set to 10 the range of t2 timing is from 396 300 96 mS to 596 500 96 mS In UBE and UBF version PWROK2 generation is the same as P...

Page 183: ...he delay time before the rising edge of PWROK and PWROK2 are t2 plus Td The length of Td is based on when the ATXPGD signal is active Once 3VCC falls below V4 or the ATXPGD signal is inactive PWROK an...

Page 184: ...TXPGD are valid Ta Figure 14 9 Timing and voltage parameters are shown in the following table SYMBOL PARAMETER MIN TYP MAX UNIT NOTE V3 3VCC Valid Voltage 2 4 2 6 2 75 V For both UBC and UBE version V...

Page 185: ...nues driving the SERIRQ low for programmable 3 to 7 clock periods This makes the total number of clocks low 4 to 8 clock periods After these clocks the host controller drives the SERIRQ high for one c...

Page 186: ...27DHG device drives the SERIRQ high During the Turn around phase the W83627DHG device leaves the SERIRQ tri stated The W83627DHG starts to drive the SERIRQ line from the beginning of IRQ0 FRAME based...

Page 187: ...rame is low for 3 clocks the Sample mode of next SERIRQ cycle is the Continuous mode Please see the diagram below for more details Stop Frame Timing with Host Using 17 SERIRQ sampling period S R T S S...

Page 188: ...egister causes the counter to load this value into the Watchdog Timer counter and start counting down The W83627DHG outputs a low signal to the WDTO pin pin 77 when a time out event occurs In other wo...

Page 189: ...SOUT or PME signal to wake up the system if any of them has any transitions There are about 16mS debounced circuit inside these 3 GPIOs and it can be disabled by programming respective bit LD9 CR FEh...

Page 190: ...Vih 2 V Vil 0 8V 1 Add a pulled down resistor at Pin 77 EN_GTL or 2 Set Configuration Register CR 2Ch bit 3 to 0 b GTL Vih 0 6 V Vil 0 4 V Default 1 No extra pulled up resistor needed or 2 Set Configu...

Page 191: ...s of LRESET in the W83627DHG are designated RSTOUT0 RSTOUT1 RSTOUT2 RSTOUT3 and RSTOUT4 All of them are powered by a 3VSB power RSTOUT0 is an open drain output buffer of LRESET This signal needs an ex...

Page 192: ...Low Byte Read Only BIT READ WRITE DESCRIPTION 7 0 Read Only Chip ID number 2Xh low byte X is the IC version CR 22h Device Power Down Default FFh BIT READ WRITE DESCRIPTION 7 Reserved 6 R W HM Power Do...

Page 193: ...n drain Default 1 SYSFANOUT is Push pull 3 R W Select output type of CPUFANOUT0 0 CPUFANOUT0 is Open drain Default 1 CPUFANOUT0 is Push pull 2 Read Only ENKBC Enable keyboard controller 0 KBC is disab...

Page 194: ...able FDC legacy mode for IRQ and DRQ selection Then DO register base address 2 bit 3 is not effective when selecting IRQ 2 R W DSPRLGRQ 0 Enable PRT legacy mode for IRQ and DRQ selection Then DCR regi...

Page 195: ...ct to enable disable decoding of BIOS ROM range FFE xxxxx 0 Enable decoding of BIOS ROM range at FFE xxxxx 1 Disable decoding of BIOS ROM range at FFE xxxxx 2 0 R W PRTMODS2 0 0xx Parallel Port Mode 1...

Page 196: ...l read The clock rate is based on the setting of CR 2Ah bits 7 6 01 Reserved 10 Reserved 11 Fast read with one dummy byte The clock rate is 33MHz If set to 11 CR 2Ah bits 7 6 must be 0 Note These two...

Page 197: ...by Pin 70 GP55 While particular ACPI functions are enabled EN_ACPI 1 GPIO3 pins pins 64 69 87 91 and 92 are disabled and the particular ACPI functions are activated SUSC FTPRST ATXPGD VSBGATE and PWRO...

Page 198: ...set by RSMRST 0 SUSLED 1 GPIO55 4 R W Pin 71 Select reset by RSMRST 0 PWROK 1 GPIO54 3 R W Pin 72 Select reset by RSMRST 0 PSON 1 GPIO53 2 R W Pin 73 Select reset by RSMRST 0 SUSB 1 GPIO52 1 R W Pin 7...

Page 199: ...ource for FDC CR 74h Default 02h BIT READ WRITE DESCRIPTION 7 3 Reserved 2 0 R W These bits select DRQ resource for FDC 000 DMA0 001 DMA1 010 DMA2 011 DMA3 1xx No DMA active CR F0h Default 8Eh BIT REA...

Page 200: ...Normal 10 1 Forced to logic 1 11 0 Forced to logic 0 1 R W DISFDDWR 0 Enable FDD write 1 Disable FDD write forces pins WE WD to stay high 0 R W SWWP 0 Normal use WP to determine whether the FDD is wri...

Page 201: ...SELECTED DATA RATE DRTS1 DRTS0 DRATE1 DRATE0 MFM FM SELDEN 1 1 1Meg 1 0 0 500K 250K 1 0 1 300K 150K 0 0 0 1 0 250K 125K 0 1 1 1Meg 1 0 0 500K 250K 1 0 1 500K 250K 0 0 1 1 0 250K 125K 0 1 1 1Meg 1 0 0...

Page 202: ...available when the base address is on 8 byte boundary CR 70h Default 07h BIT READ WRITE DESCRIPTION 7 4 Reserved 3 0 R W These bits select IRQ resource for PRT CR 74h Default 04h BIT READ WRITE DESCRI...

Page 203: ...served 3 0 R W These bits select IRQ resource for Serial Port 1 CR F0h Default 00h BIT READ WRITE DESCRIPTION 7 2 Reserved 1 0 R W 00 UART A clock source is 1 8462 MHz 24 MHz 13 01 UART A clock source...

Page 204: ...0 UART B clock source is 1 8462 MHz 24 MHz 13 01 UART B clock source is 2 MHz 24 MHz 12 00 UART B clock source is 24 MHz 24 MHz 1 00 UART B clock source is 14 769 MHz 24 MHz 1 625 CR F1h Default 00h B...

Page 205: ...to SINB IRRX 111 ASK IR Inverting IRTX SOUTB 500 KHZ clock Demodulation into SINB IRRX Note The notation is normal mode in the IR function 20 6 Logical Device 5 Keyboard Controller CR 30h Default 01h...

Page 206: ...rate selection 00 6MHz 01 8MHz 10 12MHz 11 16MHz 5 3 Reserved 2 R W 0 Port 92 disable 1 Port 92 enable 1 R W 0 Gate A20 software control 1 Gate A20 hardware speed up 0 R W 0 KBRST software control 1...

Page 207: ...utput ports the respective bits can be read and written by the pins 7 0 Read Only For input ports the respective bits can be read only from pins Write accesses will be ignored CR F6h GPIO6 Inversion R...

Page 208: ...wer LED pin is driven low 10 Power LED pin outputs 1Hz pulse with 50 duty cycle 11 Power LED pin outputs 0 25Hz pulse with 50 duty cycle 5 Reserved 4 R W WDTO count mode is 1000 times faster 0 Disable...

Page 209: ...Disable 01h Time out occurs after 1 second minute 02h Time out occurs after 2 second minutes 03h Time out occurs after 3 second minutes FFh Time out occurs after 255 second minutes CR F7h WDTO Contro...

Page 210: ...s an input port CR E1h GPIO5 Data Register Default 00h BIT READ WRITE DESCRIPTION R W GPIO5 Data register For output ports the respective bits can be read and written by the pins 7 0 Read Only For inp...

Page 211: ...WRITE DESCRIPTION 7 0 Read Only Read Clear GPIO2 Event Status Bit 7 0 corresponds to GP27 GP20 respectively 0 No active edge rising falling has been detected 1 An active edge rising falling has been d...

Page 212: ...ault 00h BIT READ WRITE DESCRIPTION R W GPIO3 Data register For output ports the respective bits can be read and written by the pins 7 0 Read Only For input ports the respective bits can only be read...

Page 213: ...ut ports the respective bits can only be read by the pins Write accesses are ignored CR F6h GPIO4 Inversion Register Default 00h BIT READ WRITE DESCRIPTION 7 0 R W GPIO4 Inversion register 0 The respe...

Page 214: ...ncer 1 Disable GP30 input de bouncer 3 Reserved 2 R W 0 GP35 trigger type edge 1 GP35 trigger type level 1 R W 0 GP31 trigger type edge 1 GP31 trigger type level 0 R W 0 GP30 trigger type edge 1 GP30...

Page 215: ...fine the combinations of the mouse wake up events Please see the following table for the details ENMDAT_UP MSRKEY MSXKEY Wake up event 1 x 1 Any button clicked or any movement 1 x 0 One click of left...

Page 216: ...cters which is indexed by CRE1 CR E3h Event Status Register Default 08h BIT READ WRITE DESCRIPTION 7 6 Reserved 5 Read Only Read Clear This status flag indicates VSB power off on 4 Read Only Read Clea...

Page 217: ...on the state before the power loss 11 User defines the state before power loss i e the last state set of CRE6 4 4 R W VSBGATE Enable bit 0 Disable 1 Enable This bit is available both for UBE and UBF v...

Page 218: ...E0 bit 4 for the details 6 Reserved 5 R W CASEOPEN Clear Control VSB Write 1 to this bit to clear CASEOPEN status This bit will not clear the status itself Please write 0 after an event is cleared The...

Page 219: ...up data register CRE2 at the index from 30h to 3eh 0 Disable the second set of the key combinations 1 Enable the second set of the key combinations 5 R W ENWIN98KEY VSB Enable Win98 keyboard dedicated...

Page 220: ...RSTOUT0 function 0 Disable RSTOUT0 1 Enable RSTOUT0 1 Reserved 0 R W EN_PME 0 Disable PME 1 Enable PME CR F3h Default 00h BIT READ WRITE DESCRIPTION 7 6 Reserved 5 R W Clear PME status of the Mouse I...

Page 221: ...ble PME interrupt of the KBC IRQ event 3 R W 0 Disable PME interrupt of the PRT IRQ event 1 Enable PME interrupt of the PRT IRQ event 2 R W 0 Disable PME interrupt of the FDC IRQ event 1 Enable PME in...

Page 222: ...GP35 event route to PME 1 Enable GP35 event route to PME 1 R W 0 Disable GP31 event route to PME 1 Enable GP31 event route to PME 0 R W 0 Disable GP30 event route to PME 1 Enable GP30 event route to...

Page 223: ...eserved CR F1h VID Data Register Default 00h BIT READ WRITE DESCRIPTION 7 0 R W VID 7 0 Data Register For Input Output both use CR F2h FAN Strapping Status Register Default 00h VCC Power BIT READ WRIT...

Page 224: ...Domain 1 Enable Bit Functions only when Agt3D1 is set to 1 0 Agent 3 always returns the relative temperature from domain 0 1 Agent 3 always returns the relative temperature from domain 1 1 R W RTD2 Ag...

Page 225: ...IPTION 7 Reserved 6 0 R W Agent 4 TBase must always be a positive value a negative value will cause abnormal temperature responses Note 1 Note 1 TBase is a temperature reference based on the experimen...

Page 226: ...gent 4 is detected and has valid FCS 1 Agent 4 cannot be detected or has invalid FCS in the previous 3 transactions 6 R W Agent 3 Absent Alert Bit 0 Agent 3 is detected and has valid FCS 1 Agent 3 can...

Page 227: ...00h BIT READ WRITE DESCRIPTION 7 0 Read Only This register shows the retrieved High Byte raw data from PECI interface CR FFh PECI Agent Relative Temperature Register Default 00h BIT READ WRITE DESCRIP...

Page 228: ...3V 5 VSS 0V PARAMETER SYM MIN TYP MAX UNIT CONDITIONS RTC Battery Quiescent Current IBAT 2 4 A VBAT 2 5 V ACPI Stand by Power Supply Quiescent Current ISB 2 0 mA VSB 3 3 V All ACPI pins are not connec...

Page 229: ...4 V IOH 12 mA Input High Leakage ILIH 10 A VIN 3 3V Input Low Leakage ILIL 10 A VIN 0V I O12ts TTL level Schmitt trigger bi directional pin with 12mA source sink capability Input Low Threshold Voltage...

Page 230: ...put High Leakage ILIH 10 A VIN 3 3V Input Low Leakage ILIL 10 A VIN 0V I OD16t TTL level bi directional pin and open drain output with 16mA sink capability Input Low Voltage VIL 0 8 V Input High Volta...

Page 231: ...stersis VTH 0 5 1 2 V VCC 3 3V Output Low Voltage VOL 0 4 V IOL 24 mA Input High Leakage ILIH 10 A VIN 3 3V Input Low Leakage ILIL 10 A VIN 0V I OD12cs CMOS level Schmitt trigger bi directional pin an...

Page 232: ...w Threshold Voltage Vt 0 5 0 8 1 1 V VCC 3 3 V Input High Threshold Voltage Vt 1 6 2 0 2 4 V VCC 3 3 V Hystersis VTH 0 5 1 2 V VCC 3 3 V Output Low Voltage VOL 0 4 V IOL 12 mA Input High Leakage ILIH...

Page 233: ...4 Open drain output pin with 24mA sink capability Output Low Voltage VOL 0 4 V IOL 24 mA OD12p3 3 3V open drain output pin with 12mA sink capability Output Low Voltage VOL 0 4 V IOL 12 mA INt TTL leve...

Page 234: ...ILIH 10 A VIN 3 3 V Input Low Leakage ILIL 10 A VIN 0 V INtsp3 3 3 V TTL level Schmitt trigger input pin Input Low Threshold Voltage Vt 0 5 0 8 1 1 V VCC 3 3 V Input High Threshold Voltage Vt 1 6 2 0...

Page 235: ...2 V VCC 3 3V Input High Leakage ILIH 10 A VIN 3 3V Input Low Leakage ILIL 10 A VIN 0 V INcsu CMOS level Schmitt trigger input pin with internal pulled up resistor Input Low Threshold Voltage Vt 0 5 0...

Page 236: ...275Vtt 0 5Vtt V Input High Voltage VIH 0 55Vtt 0 725Vtt V Output Low Voltage VOL 0 25Vtt V Output High Voltage VOH 0 75Vtt V Hysterisis VHys 0 1Vtt V I OB V4B Bi direction pin with source capability o...

Page 237: ...rsion 1 4 21 3 AC CHARACTERISTICS 21 3 1 AC Power Failure Resume Timing 1 Logical Device A CR E4h bit7 0 and CR E4h bits 6 5 are selected to OFF state OFF means always being turned off or the previous...

Page 238: ...W83627DHG Publication Release Date Aug 22 2007 226 Version 1 4 2 Logical Device A CR E4h bit7 0 and CR E4h bits 6 5 are selected to ON state ON means always being turned on or the previous state is on...

Page 239: ...ease Date Aug 22 2007 227 Version 1 4 3 Logical Device A CR E4h bit7 1 and CR E4h bits 6 5 are selected to OFF state OFF means always being turned off or the previous state is off 3VCC PSOUT PSON SUSB...

Page 240: ...n Release Date Aug 22 2007 228 Version 1 4 4 Logical Device A CR E4h bit7 1 and CR E4h bits 6 5 are selected to ON state ON means always being turned on or the previous state is on 3VCC PSOUT PSON SUS...

Page 241: ...option of user define mode for the pre defined state before AC power failure BIOS can set the pre defined state to be On or Off According to this setting the system chooses the state after the AC powe...

Page 242: ...VSBGATE t3 t4 t1 t2 VSBGATE drives low only when SUSB is active and Logical Device A CR E4h bit 4 is set to 1 VSBGATE is reset to high after PSON is active SYMBOL PARAMETER MIN MAX UNIT t1 SUSB active...

Page 243: ...ut Timing 48MHZ 24MHZ PARAMETER MIN MAX UNIT Cycle to cycle jitter 300 500 ps Duty cycle 45 55 t1 t2 t3 48MHZ 24MHZ PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 Clock cycle time 20 8 41 7 ns t2 Clock hig...

Page 244: ...PECI and SST Timing Logic 1 Minimum tH1 Maximum tH1 tBIT Next bit Logic 0 Minimum tH0 Maximum tH0 tBIT Next bit SST PECI Previous bit Previous bit SST PECI SYMBOL MIN TYP MAX UNITS Client 0 495 500 t...

Page 245: ...Version 1 4 21 3 5 SPI Timing t1 t3 t2 SCE SCK SO SI t4 t5 DESCRIPTION SYMBOL MIN TYP MAX Enable to first clock falling t1 25ns 35ns Disable after last clock rising t2 40ns 50ns Output hold time t3 5...

Page 246: ...en Stop and Start Condition 4 7 uS THD STA Hold time after Repeated Start Condition After this period the first clock is generated 4 0 uS TSU STA Repeated Start Condition setup time 4 7 uS TSU STO Sto...

Page 247: ...28 2 S STEP cycle width TSC NOTE 2 NOTE 2 NOTE 2 mS INDEX pulse width TIDX 125 250 417 500 nS RDATA pulse width TRD 40 nS WD pulse width TWD 100 185 225 475 125 210 250 500 150 235 275 525 nS Notes 1...

Page 248: ...errupt TRINT 9 1000 nS Delay from Initial IRQ Reset to Transmit Start TIRS 1 16 8 16 Baud Rate Delay from to Reset interrupt THR 175 nS Delay from Initial IOW to interrupt TSI 9 16 16 16 Baud Rate Del...

Page 249: ...ART TSINT TSTI Receiver Timing SIN RECEIVER INPUT DATA IRQ INTERNAL SIGNAL IRQ INTERNAL SIGNAL READ RECEIVER BUFFER REGISTER UART Transmitter Timing DATA BITS 5 8 PARITY STOP 1 2 START TSTI TIR TIRS T...

Page 250: ...Parallel Port Mode Parameters PARAMETER SYM MIN TYP MAX UNIT PD0 7 INDEX STROBE AUTOFD Delay from IOW t1 100 nS IRQ Delay from ACK nFAULT t2 60 nS IRQ Delay from IOW t3 105 nS IRQ Active Low in ECP an...

Page 251: ...TROBE IOW 21 3 10 2 EPP Data or Address Read Cycle Timing Parameters PARAMETER SYM MIN MAX UNIT WAIT Asserted to WRITE Deasserted t14 0 185 nS Deasserted to WRITE Modified t15 60 190 nS WAIT Asserted...

Page 252: ...d t4 40 IOR Asserted to IOCHRDY Asserted t5 0 24 nS PD Valid to SD Valid t6 0 75 nS IOR Deasserted to SD Hi Z Hold Time t7 0 40 S SD Valid to IOCHRDY Deasserted t8 0 85 nS WAIT Deasserted to IOCHRDY D...

Page 253: ...NIT WAIT Deasserted to Command Deasserted t25 60 180 nS Time out t26 10 12 nS PD Valid to WAIT Deasserted t27 0 nS PD Hi Z to WAIT Deasserted t28 0 S 21 3 10 3 EPP Data or Address Read Cycle EPP Versi...

Page 254: ...Date Aug 22 2007 242 Version 1 4 21 3 10 4 EPP Data or Address Read Cycle EPP Version 1 7 t14 t15 t17 t18 t21 t23 t24 t27 t25 t19 t28 t20 STB WRITE PD 0 7 ADDRSTB DATASTB BUSY WAIT EPP Data or Addres...

Page 255: ...Asserted t1 40 nS SD Valid to Asserted t2 10 nS IOW Deasserted to Ax Invalid t3 10 nS WAIT Deasserted to IOCHRDY Deasserted t4 0 nS Command Asserted to WAIT Deasserted t5 10 nS IOW Deasserted to IOW o...

Page 256: ...ut t20 10 12 S Command Deasserted to WAIT Asserted t21 0 nS IOW Deasserted to WRITE Deasserted and PD invalid t22 0 nS WRITE to Command Asserted t16 5 35 nS 21 3 10 6 EPP Data or Address Write Cycle E...

Page 257: ...r Address Write Cycle EPP Version 1 7 t10 t15 t16 t17 t19 t18 21 3 10 8 Parallel Port FIFO Timing Parameters PARAMETER SYMBOL MIN MAX UNIT DATA Valid to nSTROBE Active t1 600 nS nSTROBE Active Pulse W...

Page 258: ...METER SYMBOL MIN MAX UNIT nAUTOFD Valid to nSTROBE Asserted t1 0 60 nS PD Valid to nSTROBE Asserted t2 0 60 nS BUSY Deasserted to nAUTOFD Changed t3 80 180 nS BUSY Deasserted to PD Changed t4 80 180 n...

Page 259: ...TB BUSY 21 3 10 12 ECP Parallel Port Reverse Timing Parameters PARAMETER SYMBOL MIN MAX UNIT PD Valid to nACK Asserted t1 0 nS nAUTOFD Deasserted to PD Changed t2 0 nS nAUTOFD Asserted to nACK Asserte...

Page 260: ...dth 20 nS T5 Address Hold Time from WRB 0 nS T6 Address Hold Time from RDB 0 nS T7 Data Setup Time 50 nS T8 Data Hold Time 0 nS T9 Gate Delay Time from WRB 10 30 nS T10 RDB to Drive Data Delay 40 nS T...

Page 261: ...m inactive CLK transition used to time when the auxiliary device sample DATA 5 25 S T25 Time of inhibit mode 100 300 S T26 Time from rising edge of CLK to DATA transition 5 T28 5 S T27 Duration of CLK...

Page 262: ...e Timing T10 T11 T2 T4 T6 ACTIVE DATA OUT A2 CSB AEN RDB D0 D7 21 3 11 3 Send Data to K B START STOP D0 D1 D2 D3 D4 D5 D6 D7 P CLOCK KCLK SERIAL DATA KDAT T12 T14 T13 T26 21 3 11 4 Receive Data from K...

Page 263: ...D2 D3 D4 D5 D6 D7 P MCLK MDAT T25 T22 T23 T24 21 3 11 7 Receive Data from Mouse START STOP Bit D0 D1 D2 D3 D4 D5 D6 D7 P MCLK MDAT T29 T26 T27 T28 21 3 12 GPIO Timing Parameters SYMBOL PARAMETER MIN...

Page 264: ...W83627DHG Publication Release Date Aug 22 2007 252 Version 1 4 21 3 12 1 GPIO Write Timing A0 A15 IOW D0 7 GPIO 10 17 GPIO 20 25 PREVIOUS STATE VALID VALID VALID tWGO GPIO Write Timing diagram...

Page 265: ...Aug 22 2007 253 Version 1 4 21 4 LPC Timing SYMBOL DESCRIPTION MIN MAX UNIT t1 Output Valid Delay 4 11 nS t2 Float Delay 4 11 nS t3 LAD 3 0 Setup Time 14 nS t4 LAD 3 0 Hold Time 0 nS t5 LFRAME Setup T...

Page 266: ...HG Pb free package 3rd line tracking code606G9C28201234UB 606 packages made in 06 week 06 G assembly house ID G means GR A means ASE etc 9 code version 9 means code 009 C IC revision A means version A...

Page 267: ...spec Note Seating Plane See Detail F y A A 1 A 2 128 103 5 PCB layout please use the mm Symbol b c D e HD HE L y 0 A A L1 1 2 E 7 0 0 08 1 60 0 95 17 40 0 80 17 20 0 65 17 00 14 10 0 20 0 30 2 87 14 0...

Page 268: ...signal instruments combustion control instruments or for other applications intended to support or sustain life Further more Winbond products are not intended for applications wherein failure of Winbo...

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