W83627DHG
Publication Release Date: Aug, 22, 2007
-147- Version
1.4
12.2.1 Data Port (Data Swapper)
The CPU reads the contents of the printer's data latch by reading the data port.
12.2.2 Printer Status Buffer
The CPU reads the printer status by reading the printer status buffer. The bit definitions are as follows:
1
1
1
2
3
5
4
6
7
0
TMOUT
ERROR#
SLCT
PE
BUSY#
ACK#
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or in an error state. When this signal is active, the printer is busy and cannot
accept data.
Bit 6: This bit represents the current state of the printer's ACK# signal. A logical 0 means the printer has
received a character and is ready to accept another. Normally, this signal is active for approximately 5
μ
s before BUSY# stops.
Bit 5: A logical 1 means the printer has detected the end of paper.
Bit 4: A logical 1 means the printer is selected.
Bit 3: A logical 0 means the printer has encountered an error condition.
Bit 1, 2: Reserved. These two bits are always read as logical 1.
Bit 0: This bit is only valid in EPP mode. A logical 1 indicates that a 10-
μ
s time-out has occurred on the
EPP bus; a logical 0 means that no time-out error has occurred. Writing a logical 1 to this bit clears the
time-out status bit; writing a logical 0 has no effect.
12.2.3 Printer Control Latch and Printer Control Swapper
The CPU reads the contents of the printer control latch by reading the printer control swapper. The bit
definitions are as follows:
1
1
1
2
3
4
5
6
7
0
STROBE
AUTO FD
SLCT IN
IRQ ENABLE
DIR
INIT#
Bit 7, 6: These two bits are always read as logical 1. They can be written.
Bit 5: Direction control bit
Summary of Contents for W83627DHG
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