W83627DHG
Publication Release Date: Aug, 22, 2007
-234- Version
1.4
21.3.6 SMBus Timing
SMBCLK
SMBDAT
P
S
P
S
T
BUF
T
HD:STA
T
LOW
T
R
T
HD:DAT
T
HIGH
T
F
T
SU:DAT
T
SU:STA
T
SU:STO
SYMBOL PARAMETER MIN.
MAX.:
UNITS
T
BUF
Bus Free Time between Stop and
Start Condition
4.7 -
uS
T
HD:STA
Hold time after (Repeated) Start
Condition. After this period, the
first clock is generated
4.0 -
uS
T
SU:STA
Repeated Start Condition setup
time
4.7 -
uS
T
SU:STO
Stop Condition setup time
4.0
-
uS
T
HD:DAT
Data hold time
300
-
nS
T
SU:DAT
Data setup time
250
-
nS
T
LOW
Clock low period
4.7
-
uS
T
HIGH
Clock high period
4.0
50
uS
T
F
Clock/Data Falling Time
-
300
nS
T
R
Clock/Data Rising Time
-
1000
nS
Summary of Contents for W83627DHG
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