W83627DHG
Publication Release Date: Aug, 22, 2007
-170- Version
1.4
Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR[E6h] bits 3 ~1.
LOGICAL DEVICE A,
CR[E6H] BIT
DEFINITION
3
PWROK_DEL (first stage)
(VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
2~1
PWROK_DEL
(VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
01: Delay 32 mS
10: 96 mS
11: Delay 250 mS
For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2
timing is from 396(300 + 96) mS to 596(500 + 96) mS.
* In UBE and UBF version, PWROK2 generation is the same as PWROK generation.
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and
UBF Version Only
PWROK and PWROK2 signals as well as ATXPGD and FTPRST# input signals are interrelated.
Once the FTPRST# signal changes from high to low then to high, the PWROK and PWROK2 signals
will have the same transition after 28mS ~ 39mS delay.
The relation and parameter are illustrated in the
following figure and table.
t3
T
L
FTPRST#
PWROK/PWROK2
3VCC
T
L
Figure 14.7
Summary of Contents for W83627DHG
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