W83627DHG
Publication Release Date: Aug, 22, 2007
-141- Version
1.4
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high after HSR was read by
the CPU.
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read by the CPU.
11.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
1
2
3
4
5
6
7
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level of the receiver FIFO interrupt. The active level is
the number of bytes that must be in the receiver FIFO to generate an interrupt.
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0 0
01
0 1
04
1 0
08
1 1
14
Bit 4, 5: Reserved
Bit 3: When this bit is set to logical 1, DMA mode changes from mode 0 to mode 1 if UFR bit 0 = 1.
Bit 2: Setting this bit to logical 1 resets the TX FIFO counter logic to its initial state. This bit is
automatically cleared afterwards.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit is
automatically cleared afterwards.
Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits
are programmed.
Summary of Contents for W83627DHG
Page 2: ......
