W83627DHG
Publication Release Date: Aug, 22, 2007
-129- Version
1.4
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits in LD0 CRF2. Which two bits are reflected depends on the last
drive selection in the DO register.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of LD0 CRF1, bits 7 and 6.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved for the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0 0
None
0 1
1
1 0
2
1 1
3
10.2.5 Main Status Register (MS Register) (Read base a 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
Reserved.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register
is ready to send or receive data to or from the processor.
7
6
5
4
3
2
1
0
Reserved.
Reserved.
10.2.6 Data Rate Register (DR Register) (Write base a 4)
The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-AT
and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR
register. As a result, the real data rate is determined by the most recent write to either the DR or CC
register. The bit definitions for this register are as follows:
Summary of Contents for W83627DHG
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