W83627DHG
Publication Release Date: Aug, 22, 2007
-142- Version
1.4
11.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status.
1
2
3
4
5
6
7
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
0
0
Bit 7, 6: These two bits are set to logical 1 when UFR, bit 0 = 1.
Bit 5, 4: These two bits are always logical 0.
Bit 3: In 16450 mode, this bit is logical 0. In 16550 mode, bits 3 and 2 are set to logical 1 when a
time-out interrupt is pending. See the table below.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit is set to logical 0.
ISR
INTERRUPT SET AND FUNCTION
Bit 3 Bit 2 Bit 1 Bit 0
Interrupt
priority
Interrupt Type
Interrupt Source
Clear Interrupt
0
0
0
1
-
-
No Interrupt pending
-
0 1 1 0 First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0
1
0
0
Second
RBR Data Ready
1. RBR data ready
2. FIFO interrupt active level
reached
1. Read RBR
2. Read RBR until FIFO
data under active level
1 1 0 0 Second FIFO
Data
Timeout
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
0
0
1
0
Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0 0 0 0 Fourth Handshake
status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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