W83627DHG
Publication Release Date: Aug, 22, 2007
-164- Version
1.4
14. POWER MANAGEMENT EVENT
The PME# (pin 86) signal is connected to the South Bridge and is used to wake up the system from S1
~ S5 sleeping states.
One control bit and four registers in the W83627DHG are associated with the PME function. The
control bit is at Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this
bit is set to “0”, the W83627DHG won’t output any PME signal when any of the wake-up events has
occurred and is enabled. The four registers are divided into PME status registers and PME interrupt
registers of wake-up events
Note.1
.
1) The PME status registers of wake-up event:
-
At Logical Device A, CR[F3h] and CR[F4h]
-
Each wake-up event has its own status
-
The PME status should be cleared by writing a “1” before enabling its corresponding bit in the
PME interrupt registers
2) The PME interrupt registers of wake-up event:
-
At Logical Device A, CR[F6h] and CR[F7h]
-
Each wake-up event can be enabled / disabled individually to generate a PME# signal
Note.1
PME wake-up events that the W83627DHG supports include:
z
Mouse IRQ event
z
Keyboard IRQ event
z
Printer IRQ event
z
Floppy IRQ event
z
UART A IRQ event
z
UART B IRQ event
z
Hardware Monitor IRQ event
z
WDTO# event
z
RIB (UARTB Ring Indicator) event
14.1 Power Control Logic
This chapter describes how the W83627DHG implements its ACPI function via these power control
pins: PSIN# (Pin 68), PSOUT# (Pin 67), SUSB# (i.e. SLP_S3#; Pin 73) and PSON# (Pin 72). The
following figure illustrates the relationships.
IOCLK
VCC ON
3VCC
W83627DHG
3VSB/VBAT
South Bridge
Power
Supply
PSON#
PSON#
PWRBTN#
SUSB#
SLP_S3#
PSOUT#
PSIN#
48 / 24 MHz
IOCLK
VCC ON
VCC ON
3VCC
W83627DHG
3VSB/VBAT
South Bridge
Power
Supply
PSON#
PSON#
PWRBTN#
SUSB#
SLP_S3#
PSOUT#
PSIN#
48 / 24 MHz
Figure 14.1
Summary of Contents for W83627DHG
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