Index
Index-12
memory map
boot configuration
memory mapped operation
memory mapped registers
memory request priority
memory type field (MTYPE)
memory
external interface
types and ’C6202
widths
memory–mapped registers
million instructions per second (MIPS)
mode
asynchronous
synchronous host port
modes
16–bit ROM
asynchronous host port
asynchronous I/O
cache
cache enabled
destination update mode (DUM)
FIFO output enable signal
freeze or bypass
host port (mutually exclusive)
host port interface
I/O port (non–exclusive)
internal program memory
level 1 data cache
mapped
power down
pulse and clock
slave
source update mode
synch FIFO
synchronous FIFO
monitoring , flag
MTYPE field
MTYPE, write hold, and read hold bit fields
multichannel buffered serial port (McBSP,
introduction
multichannel buffered serial port (McBSP)
8-4
channel enable diagram
channel enable register
CLKP bit
clock configuration
clocking examples
companding data formats
companding DLB method
companding hardware
companding nonDLB method
configuration
control register
CPU interrupts
data delay
data packing
data reception
data transmission
double-rate clock
double-rate ST-BUS clock
element length
end-of-block interrupt
end-of-frame interrupt
exception conditions
features
frame configuration
frame frequency
frame generation
frame sync signal generation
frame synch ignore bits
interface signals
multi hannel enable
multichannel selection operation
multiphase frame example: AC97
overrun
pins as general-purpose I/O
programmable clock
RDATDLY
receive control register
frame synchronization
receive operation
registers
reset
RFULL
rsyncherr
sample rate generator
reset procedure
sample rate generator register (SRGR)
sample rate generator reset
single-rate ST-BUS clock
SPI protocol (CLKSTP)
standard operation
transmit control register
transmit data companding
transmit ready
transmit with data overwrite
unexpected frame sync pulse