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Texas Instruments TMS320C6201, Reference Manual

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Programmable Clock and Framing

11-57

Multichannel Buffered Serial Ports

11.5.2 Data Clock Generation

When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1), the data
clocks (CLK(R/X)) are driven by the internal sample rate generator output
clock, CLKG. You can select for the receiver and transmitter from a variety of
data bit clocks including:

-

The input clock to the sample rate generator, which can be either the inter-
nal clock source or a dedicated external clock source (CLKS). The internal
clock source for the ’C6211/C6711 is CPU clock, while the internal clock
source for ’C6211/C6711 is CPU/2 clock (half of the CPU clock frequency).

-

The input clock source (internal clock source or external clock CLKS) to
the sample rate generator can be divided down by a programmable value
(CLKGDV) to drive CLKG.

Regardless of the source to the sample rate generator, the rising edge of
CLKSRG (see Figure 11–38) generates CLKG and FSG (see section
11.5.2.3).

11.5.2.1 Input Clock Source Mode: CLKSM

The CLKSM bit in the SRGR selects either the CPU clock (CLKSM = 1) or the
external clock input (CLKSM = 0), CLKS, as the source for the sample rate
generator input clock. Any divide periods are divide-downs calculated by the
sample rate generator and are timed by this input clock selection. The McBSP
cannot run faster than half of the CPU clock frequency. Therefore, when
CLKSM = 1, the minimum value of CLKGDV should be 1 for the
’C6201/C6202/C6701. For the ’C6211/C6711, even if CLKSM = 1 you can set
CLKGDV to the minimum of 0 because a CPU/2 clock drives the sample rate
generator.

11.5.2.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV

The first divider stage generates the serial data bit clock from the input clock.
This divider stage uses a counter that is preloaded by CLKGDV and that con-
tains the divide ratio value. The output of this stage is the data bit clock that
is output on the sample rate generator output, CLKG, and that serves as the
input for the second and third divider stages.

CLKG has a frequency equal to 1/(1) of the sample rate generator
input clock. Thus, the sample-rate generator input clock frequency is divided
by a value between 1 and 256. When CLKGDV is odd or equal to 0, the CLKG
duty cycle is 50%. When CLKGDV is an even value (2p) the high state duration
is p + 1 cycles and the low state duration is p cycles.

Summary of Contents for TMS320C6201

Page 1: ...TMS320C6000 Peripherals Reference Guide Literature Number SPRU190C April 1999 Printed on Recycled Paper ...

Page 2: ...NED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be dir...

Page 3: ...s of digi tal signal processors make up the TMS320C6000 platform of the TMS320 family of digital signal processors The C62x devices are fixed point DSPs and the C67x devices are floating point DSPs The TMS320C6000 C6000 is the first DSP to use the VelociTI architecture a high performance advanced VLIW very long instruction word architecture The VelocTI archite chure makes the C6x an excellent choi...

Page 4: ...t Reference Guide literature number SPRU189 describes the C6000 CPU architecture instruction set pipeline and interrupts for these digital signal processors TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C6000 Assembly Language Tools User s Guide literature number SPRU1...

Page 5: ...ngs for the device TMS320C6211 Digital Signal Processor Data Sheet literature number SPRS073 describes the features of the TMS320C6211 fixed point DSP and provides pinouts electrical specifications and timings for the de vice TMS320C6711 Digital Signal Processor Data Sheet literature number SPRS088 describes the features of the TMS320C6711 fixed point DSP and provides pinouts electrical specificat...

Page 6: ...ning Helpline Fax 49 81 61 80 40 10 Asia Pacific Literature Response Center 852 2 956 7288 Fax 852 2 956 2200 Hong Kong DSP Hotline 852 2 956 7268 Fax 852 2 956 1002 Korea DSP Hotline 82 2 551 2804 Fax 82 2 551 2828 Korea DSP Modem BBS 82 2 551 2914 Singapore DSP Hotline Fax 65 390 7179 Taiwan DSP Hotline 886 2 377 1450 Fax 886 2 377 2718 Taiwan DSP Modem BBS 886 2 376 2592 Taiwan DSP Internet BBS...

Page 7: ...des program memory organization cache modes DMA and peripheral bus operation 2 1 Program Memory Controller 2Ć2 2 2 Internal Program Memory 2Ć3 2 2 1 Internal Program Memory Modes 2Ć3 2 2 2 Cache Architecture 2Ć4 2 3 DMA Controller Access to Program Memory 2Ć6 2 4 Data Memory Controller 2Ć7 2 5 Data Memory Access 2Ć8 2 6 Internal Data Memory Organization 2Ć9 2 6 1 TMS320C6201 Revision 2 2Ć9 2 6 2 T...

Page 8: ... Access DMA Controller 5Ć1 Describes the direct memory access controller operation 5 1 Overview 5Ć2 5 2 DMA Registers 5Ć5 5 2 1 DMA Channel Control Registers 5Ć8 5 3 Memory Map 5Ć12 5 4 Initiating a Block Transfer 5Ć13 5 4 1 DMA Autoinitialization 5Ć13 5 5 Transfer Counting 5Ć16 5 6 Synchronization Triggering DMA Transfers 5Ć17 5 6 1 Latching of DMA Channel Event Flags 5Ć18 5 6 2 Automated Event C...

Page 9: ... Parameter RAM PaRAM 6Ć9 6 5 1 EDMA Transfer Parameter Entry 6Ć12 6 6 EDMA Transfer Parameters 6Ć13 6 6 1 Options Parameter 6Ć13 6 6 2 SRC DST Address 6Ć14 6 6 3 Element Count 6Ć15 6 6 4 Frame Array Count 6Ć15 6 6 5 Element Frame Array Index 6Ć15 6 6 6 Element Count Reload 6Ć15 6 6 7 Link Address 6Ć16 6 7 Initiating an EDMA Transfer 6Ć17 6 7 1 Synchronization of EDMA Transfers 6Ć17 6 8 Types of ED...

Page 10: ... Bus Access 7Ć12 7 3 HPI Registers 7Ć16 7 3 1 HPI Control Register HPIC 7Ć16 7 3 2 Software Handshaking Using HRDY and FETCH 7Ć17 7 3 3 Host Device Using DSPINT to Interrupt the CPU 7Ć18 7 3 4 CPU Using HINT to Interrupt the Host 7Ć18 7 4 Host Access Sequences 7Ć19 7 4 1 Host Initialization of HPIC and HPIA 7Ć19 7 4 2 HPID Read Access Without Autoincrement 7Ć20 7 4 3 HPID Read Access With Autoincr...

Page 11: ...access off chip memory 9 1 Overview 9Ć2 9 2 Resetting the EMIF 9Ć8 9 3 EMIF Registers 9Ć9 9 3 1 Global Control Register 9Ć9 9 3 2 EMIF CE Space Control Registers 9Ć12 9 3 3 EMIF SDRAM Control Register 9Ć15 9 3 4 EMIF SDRAM Timing Register 9Ć17 9 3 5 TMS320C6211 C6711 SDRAM Extension Register 9Ć18 9 4 SDRAM Interface 9Ć20 9 4 1 SDRAM Initialization 9Ć25 9 4 2 Monitoring Page Boundaries 9Ć25 9 4 3 S...

Page 12: ...Serial Ports 11Ć1 Describes the features and operation of the two multichannel buffered serial ports 11 1 Features 11Ć2 11 2 McBSP Interface Signals and Registers 11Ć3 11 2 1 Serial Port Configuration 11Ć7 11 2 2 Receive and Transmit Control Registers RCR and XCR 11Ć14 11 3 Data Transmission and Reception 11Ć18 11 3 1 Resetting the Serial Port R X RST GRST and RESET 11Ć18 11 3 2 Determining Ready ...

Page 13: ...egister 12Ć6 12 2 3 Timer Counter Register 12Ć6 12 3 Resetting the Timers and Enabling Counting GO and HLD 12Ć7 12 4 Timer Counting 12Ć8 12 5 Timer Clock Source Selection CLKSRC 12Ć8 12 6 Timer Pulse Generation 12Ć9 12 7 Boundary Conditions in the Control Registers 12Ć11 12 8 Timer Interrupts 12Ć11 12 9 Emulation Operation 12Ć11 13 Interrupt Selector and External Interrupts 13Ć1 Describes the inte...

Page 14: ...d Logic 15Ć4 15 5 JTAG Emulator Cable Pod Signal Timing 15Ć5 15 6 Emulation Timing Calculations 15Ć6 15 7 Connections Between the Emulator and the Target System 15Ć8 15 7 1 Buffering Signals 15Ć8 15 7 2 Using a Target System Clock 15Ć10 15 7 3 Configuring Multiple Processors 15Ć11 15 8 Mechanical Dimensions for the 14 Pin Emulator Connector 15Ć12 15 9 Emulation Design Considerations 15Ć14 15 9 1 U...

Page 15: ...7 4 1 TMS320C6211 C6711 Block Diagram 4Ć2 4 2 TMS320C6211 Internal Memory Block Diagram 4Ć3 4 3 TMS320C6711 Internal Memory Block Diagram 4Ć4 4 4 L1P Address Allocation 4Ć6 4 5 L1P Direct Mapped Cache Diagram 4Ć7 4 6 L1P Flush Base Address Register Fields L1PFBAR 4Ć8 4 7 L1P Flush Word Count Register Fields L1PFWC 4Ć8 4 8 L1D Address Allocation 4Ć9 4 9 L1D 2 Way Set Associative Cache Diagram 4Ć11 ...

Page 16: ...gister EER 6Ć7 6 5 Event Clear Register ECR 6Ć8 6 6 Event Set Register ESR 6Ć8 6 7 Parameter Storage for an EDMA Event 6Ć12 6 8 Options Bit Fields 6Ć13 6 9 Non 2D R W Sync EDMA Transfer Without Frame Sync 6Ć21 6 10 Non 2D EDMA Transfer With Frame Sync 6Ć22 6 11 Read Write Synchronized 2 D Transfer No Frame Sync 6Ć23 6 12 Frame Synchronized 2 D Transfer 6Ć23 6 13 Linked EDMA Transfer 6Ć25 6 14 Chan...

Page 17: ...ter Disabled 8Ć31 8 21 External Device Requests the Bus From the TMS320C6202 Using XBOFF 8Ć33 8 22 The Expansion Bus Master Writes a Burst of Data to the TMS320C6202 8Ć37 8 23 The Bus Master Reads a Burst of Data From the TMS320C6202 8Ć39 8 24 Timing Diagrams for Asynchronous Host Port Mode of the Expansion Bus 8Ć43 8 25 Timing Diagrams for Bus Arbitration XHOLD XHOLDA Internal Bus Arbiter Enabled...

Page 18: ...02 C6701 SBSRAM Interface 9Ć44 9 31 TMS320C6211 C6711 SBSRAM interface 9Ć44 9 32 SBSRAM Four Word Read 9Ć45 9 33 TMS320C6211 C6711 SBSRAM Six Word Read 9Ć46 9 34 TMS320C6201 C6202 C6701 SBSRAM Four Word Write 9Ć48 9 35 TMS320C6211 C6711 SBSRAM Write 9Ć48 9 36 TMS6201 C6202 C6701 EMIF to 32 bit SRAM Interface 9Ć50 9 37 TMS320C6211 C6711 EMIF to 16 bit SRAM Big Endian 9Ć50 9 38 EMIF to 8 Bit ROM Int...

Page 19: ...ty Avoided 11Ć46 11 31 Response to Transmit Frame Synchronization 11Ć47 11 32 Unexpected Transmit Frame Synchronization Pulse 11Ć48 11 33 Companding Flow 11Ć50 11 34 Companding Data Formats 11Ć51 11 35 Transmit Data Companding Format in DXR 11Ć51 11 36 Companding of Internal Data 11Ć52 11 37 Clock and Frame Generation 11Ć53 11 38 Sample Rate Generator 11Ć54 11 39 Sample Rate Generator Register SRG...

Page 20: ...14 2 PWRD Field of the CSR Register 14Ć3 14 3 Peripheral Power Down Control Fields for the TMS320C6202 14Ć6 15 1 14 Pin Header Signals and Header Dimensions 15Ć2 15 2 JTAG Emulator Cable Pod Interface 15Ć4 15 3 JTAG Emulator Cable Pod Timings 15Ć5 15 4 Target System Generated Test Clock 15Ć10 15 5 Multiprocessor Connections 15Ć11 15 6 Pod Connector Dimensions 15Ć12 15 7 14 Pin Connector Dimensions...

Page 21: ...3 4 Internal Program RAM Address Mapping in Cache Mode 3Ć5 3 5 Internal Data RAM Address Mapping 3Ć7 4 1 TMS320C6211 C6711 Internal Memory Configurations 4Ć2 4 2 TMS320C6211 C6711 Cache Architectures 4Ć2 4 3 Internal Memory Control Register Addresses 4Ć5 4 4 Level 1 Program Cache Mode Settings 4Ć6 4 5 Level 1 Data Cache Mode Settings 4Ć10 4 6 Cache Configuration Register Field Description 4Ć13 4 7...

Page 22: ...s to HPI With Autoincrement HWOB 0 7Ć23 7 13 Data Write Access to HPI Without Autoincrement HWOB 1 7Ć24 7 14 Data Write Access to HPI Without Autoincrement HWOB 0 7Ć24 7 15 Write Access to HPI With Autoincrement HWOB 1 7Ć25 7 16 Write Access to HPI With Autoincrement HWOB 0 7Ć26 8 1 Expansion Bus Signals 8Ć5 8 2 Expansion Bus Memory Mapped Registers 8Ć6 8 3 Expansion Bus Host Port Registers 8Ć7 8 ...

Page 23: ...s to EA Mapping for 32 bit Interface 9Ć33 9 15 TMS320C6201 C6202 C6701 SDRAM Timing Parameters 9Ć34 9 16 SBSRAM in Linear Burst Mode 9Ć43 9 17 EMIF SBSRAM Pins 9Ć45 9 18 EMIF Asynchronous Interface Pins 9Ć49 9 19 Byte Address to EA Mapping for Asynchronous Memory Widths 9Ć52 9 20 TMS320C6201 C6202 C6701 EMIF Prioritization of Requests 9Ć61 9 21 TMS320C6211 C6711 EMIF Prioritization of Requests 9Ć6...

Page 24: ...11Ć81 11 22 Configuration of Pins as General Purpose I O 11Ć87 12 1 Timer Registers 12Ć4 12 2 Timer Control Register Field Descriptions 12Ć4 12 3 Timer GO and HLD Field Operation 12Ć7 12 4 TSTAT Parameters in Pulse and Clock Modes 12Ć10 13 1 TMS320C6201 C6202 C6701 Available Interrupts 13Ć3 13 2 TMS320C6211 C6711 Available Interrupts 13Ć4 13 3 Interrupt Selector Registers 13Ć7 13 4 Default Interru...

Page 25: ...le instructions during a single clock cycle Parallelism is the key to extremely high performance taking these DSPs well beyond the performance capabilities of traditional designs This chapter introduces the TMS320 family of DSPs and the C6000 platform of this family and it describes the features memory and peripherals of the C6000 devices Topic Page 1 1 The TMS320 Family Overview 1 2 1 2 Overview ...

Page 26: ...Year Today the TMS320 family consists of these generations C1x C2x C27x C5x and C54x C55x fixed point DSPs C3x and C4x floating point DSPs and C8x multiprocessor DSPs Now there is a new generation of DSPs the TMS320C6000 platform with performance and features that are reflective of Texas Instruments commitment to lead the world in DSP solutions 1 1 2 Typical Applications for the TMS320 Family Tabl...

Page 27: ...ntrol Power line monitoring Robotics Security access Instrumentation Medical Military Digital filtering Function generation Pattern matching Phase locked loops Seismic processing Spectrum analysis Transient analysis Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Image processing Missile guidance Navigation Radar processing Radio frequency mod...

Page 28: ...unction applications such as Pooled modems Wireless local loop base stations Remote access servers RAS Digital subscriber loop DSL systems Cable modems Multichannel telephony systems The TMS320C6000 platform is also an ideal solution for exciting new applica tions for example Personalized home security with face and hand fingerprint recognition Advanced cruise control with GPS navigation and accid...

Page 29: ...acteristics Features of the C6000 devices include Advanced VLIW CPU with eight functional units including two multipliers and six arithmetic units J Executes up to eight instructions per cycle for up to ten times the per formance of other DSPs J Allows designers to develop highly effective RISC like code for rapid development Instruction packing J Gives code size equivalence for eight instructions...

Page 30: ...ed through the external memory interface EMIF TMS320C6201 C6202 C6701 The C6201 C6202 and C6701 each have separate data and program memories The internal program memory can be mapped into the CPU address space or operated as a program cache A 256 bit wide path is provided from to the CPU to allow a continuous stream of eight 32 bit instructions for maximum performance Data memory is accessed throu...

Page 31: ...a cache L1D controller provides the interface between the CPU and the L1D The L1D is a dual ported memory which allows simulta neous access by both sides of the CPU On a miss to either L1D or L1P the request is passed to the L2 controller The L2 controller facilitates The CPU and the enhanced direct memory access EDMA controller ac cesses to the internal memory and performs the necessary arbitrati...

Page 32: ...nfiguration Y Y Y Y Y Multichannel buffered serial ports McBSPs 2 3 2 2 2 Interrupt selector Y Y Y Y Y 32 bit timers 2 2 2 2 2 Power down logic Y Y Y Y Y The user accessible peripherals are configured via a set of memory mapped control registers The peripheral bus controller performs the arbitration for ac cesses of on chip peripherals The Boot Configuration logic is interfaced through external si...

Page 33: ...on bus Direct memory access controller DMA Timer 0 Timer 1 Program memory cache controller Internal program memory L1 S1 M1 D1 D2 M2 S2 L2 A register file Data path A B register file Interrupt control CPU Instruction fetch Instruction dispatch Instruction decode In circuit emulation Control registers Data memory controller Internal data memory Power down logic DMA buses Program bus Data bus Expans...

Page 34: ...troller performs the same functions as the DMA controller The EDMA has sixteen programmable channels as well as a RAM space to hold multiple configurations for future transfers HPI The HPI is a parallel port through which a host processor can directly ac cess the CPU s memory space The host device has ease of access because it is the master of the interface The host and the CPU can exchange inform...

Page 35: ...n memory automatically with the aid of the DMA EDMA controller It also has multichannel capability compatible with the T1 E1 SCSA and MVIP networking standards Like its predecessors it provides Full duplex communication Double buffered data registers that allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry standard codecs analog int...

Page 36: ...rupts available The interrupt selector allows you to choose which 12 interrupts your system needs The interrupt selector also allows you to change the polarity of external interrupt inputs Power down The power down logic allows reduced clocking to reduce pow er consumption Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another By preventing so...

Page 37: ...nd access of program memory through the DMA controller for the TMS320C6201 C6701 Topic Page 2 1 Program Memory Controller 2 2 2 2 Internal Program Memory 2 3 2 3 DMA Controller Access to Program Memory 2 6 2 4 Data Memory Controller 2 7 2 5 Data Memory Access 2 8 2 6 Internal Data Memory Organization 2 9 2 7 Peripheral Bus 2 21 Chapter 2 ...

Page 38: ...nterface EMIF Manages the internal program memory when it is configured as cache Figure 2 1 TMS320C6201 C6701 Program Memory Controller in the Block Diagram Program memory cache Program memory controller EMIF PLL Host port DMA controller Peripheral bus controller EMIF control DMA control HPI control McBSPs Interrupt selector Timers Data memory controller Data memory CPU core 2 Data path 1 Data pat...

Page 39: ...y controller See Chapter 7 Boot Configuration Reset and Memory Map for informa tion about how to select the memory map Cache enabled In cache enabled mode any initial program fetch at an ad dress causes a cache miss In a cache miss the fetch packet is loaded from the external memory interface EMIF and stored in the internal cache memory one 32 bit instruction at a time While the fetch packet is be...

Page 40: ...d use the follow ing assembly routine to ensure correct operation of the PMEMC This routine enables the cache To change the PMEMC operation mode to a state other than cache enable you should modify line four of the routine to correspond the the value of PCC that you want moved into B5 For example to put the cache into mapped mode 0000h should be moved into B5 The CPU regis ters used in this exampl...

Page 41: ...his RAM contains a 10 bit tag plus a valid bit that is used to record frame validity information Figure 2 2 Logical Mapping of Cache Address 31 26 25 16 15 5 4 0 Outside external range assumed to be 0 Tag Block offset Fetch packet alignment assumed 0 2 2 2 2 Cache Flush A dedicated valid bit in each address location of the tag RAM indicates whether the contents of the corresponding cache frame is ...

Page 42: ...requests that occur after arbitration and while a DMA controller access is in progress the CPU in curs one wait state per DMA controller access The maximum throughput to the DMA is one access every other cycle In a cache mode a DMA controller write is ignored by the program memory controller and a read returns an undefined value For both DMA reads and writes in cache modes the DMA controller is si...

Page 43: ...on chip peripherals through the peripheral bus controller The peripheral bus controller performs arbitration between the CPU and DMA for the on chip peripherals Figure 2 3 TMS320C6x Block Diagram Program memory cache Program memory controller EMIF PLL Host port DMA controller Peripheral bus controller EMIF control DMA control HPI control MCSPs Interrupt selector Timers Data memory Data memory cont...

Page 44: ...es to internal data memory The CPU cannot access internal program memory through the data memory controller The CPU sends requests to the data memory controller through the two address buses DA1 and DA2 Store data is transmitted through the CPU data store buses ST1 and ST2 Load data is received through the CPU data load buses LD1 and LD2 The CPU data requests are mapped based on address to either ...

Page 45: ...controller can simulta neously access data that resides in different banks This organization allows the two CPU data ports A and B to simultaneously access neighboring 16 bit data elements inside the block without a resource conflict Table 2 2 Data Memory Organization TMS320C6201 Revision 2 Bank 0 Bank 1 Bank 2 Bank 3 First address 80000000 80000008 S S S 8000FFF0 80000001 80000009 S S S 8000FFF1 ...

Page 46: ...ta memory controller DMA controller External memory interface Peripheral bus controller 32 32 32 Bank 0 Bank 1 Bank 2 Bank 3 64 K bytes 16 16 16 16 Side A Side B C6201 CPU 32 32 32 32 Control DA2 address ST2 store data LD2 load data Control DA1 address ST1 store data LD1 load data 0 1 2 3 4 5 6 7 8 9 A B C D E F 8000 0000 8000 FFFF ...

Page 47: ...s LSBs when the two accesses involve data in the same block This organization also allows the two CPU data ports A and B to simultaneously access neighboring 16 bit data elements inside the block without a resource conflict Table 2 3 Data Memory Organization TMS320C6201 Revision 3 Bank 0 Bank 1 Bank 2 Bank 3 First address Block 0 80000000 80000008 S S S 80007FF0 80000001 80000009 S S S 80007FF1 80...

Page 48: ...nk 3 Bank 2 Bank 1 Bank 0 DMA controller Peripheral bus controller External memory interface 16 16 16 16 Data memory controller DMEMC 32 32 32 16 16 16 16 Side A Side B C6201 CPU 32 32 32 32 Control DA2 address ST2 store data LD2 load data Control DA1 address ST1 store data LD1 load data 8000 0000 8000 7FFF 8000 FFFF 8000 8000 0 2 1 3 4 6 5 7 8 A 9 B C E D F 0 2 1 3 4 6 5 7 8 A 9 B C E D F ...

Page 49: ...o pay attention to address LSBs when two ac cesses involve data in the same block This organization also allows the two CPU data ports A and B to simultaneously access neighboring 16 bit data elements inside the same block without a resource conflict Table 2 4 Data Memory Organization Bank 0 Bank 1 Bank 2 Bank 3 First address Block 0 80000000 80000001 80000002 80000003 80000004 80000005 80000006 8...

Page 50: ...ck 0 32K bytes 32K bytes Block 1 Bank 7 Bank 6 Bank 5 Bank 4 DMA controller Peripheral bus controller External memory interface 16 16 16 16 Data memory controller DMEMC 32 32 32 16 16 16 16 Side A Side B C6701CPU 32 64 64 32 Control DA2 address ST2 store data LD2 load data Control DA1 address ST1 store data LD1 load data 8000 FFFF 8000 8000 8000 0000 8000 7FFF D C B A 0 1 2 3 4 5 6 7 9 8 F E D C B...

Page 51: ...bit bytes 16 bit halfwords and 32 bit words The data memory controller performs arbitration individually for each 16 bit bank Although arbitration is performed on 16 bit wide banks the banks have byte enables to support byte wide accesses However a byte ac cess prevents the entire 16 bits containing the byte from simultaneously being used by another access As long as multiple requesters access dat...

Page 52: ...oad occurs before any store access A load in parallel with a store always has priority over the store If both the load and the store access the same resource for example the EMIF or peripheral bus internal memory block the load always occurs before the store If both accesses are stores the access from DA1 takes precedence over the access from DA2 If both ac cesses are loads the access from DA2 tak...

Page 53: ... 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0000 0001 0010 0011 0100 0101 B 0110 B y 0111 y t e 1000 e 1001 1010 1011 1100 1101 1110 1111 0000 H 0010 H a 0100 a l f 0110 f w o 1000 o r d 1010 d 1100 1110 W 0000 W o 0100 r d 1000 d 1100 D W 000...

Page 54: ...ired by the CPU the CPU is held off until all DMA accesses to the necessary blocks finish In contrast if the CPU has higher priority PRI 0 then the DMA access is postponed until the both CPU data ports stop accessing that bank In this con figuration a DMA access request never causes a wait state 2 6 7 Data Endianness Two standards for data ordering in byte addressable microprocessors exist Little ...

Page 55: ... Register Result LDW 00 BA987654h BA987654h LDH 00 FFFFBA98h 00007654h LDHU 00 0000BA98h 00007654h LDH 10 00007654h FFFFBA98h LDHU 10 00007654h 0000BA98h LDB 00 FFFFFFBAh 00000054h LDBU 00 000000BAh 00000054h LDB 01 FFFFFF98h 00000076h LDBU 01 00000098h 00000076h LDB 10 00000076h FFFFFF98h LDBU 10 00000076h 00000098h LDB 11 00000054h FFFFFFBAh LDBU 11 00000054h 000000BAh Note The contents of the w...

Page 56: ... x000 before the ST instruction executes is FEDC BA98 7654 3210h Table 2 7 Memory Contents After Little Endian or Big Endian Data Stores TMS320C6201 C6701 Instruction Address Bits 1 0 Big Endian Memory Result Little Endian Memory Result STW 00 BA98 7654h BA98 7654h STH 00 7654 1970h 0112 7654h STH 10 0112 7654h 7654 1970h STB 00 5412 1970h 0112 1954h STB 01 0154 1970h 0112 5470h STB 10 0112 5470h ...

Page 57: ...erly Any side effects caused by a peripheral control register read occur regardless of which bytes are read In contrast for byte or halfword writes the values the CPU and the DMA controller only provide correct values in the enabled bytes The values that are always correct are shown in Table 2 8 Undefined results are written to the nonenabled bytes If you are not concerned about the values in the ...

Page 58: ...ipheral bus controller performs arbitration between the CPU and the DMA controller for the peripheral bus Like internal data access the PRI bits in the DMA controller determine the priority between the CPU and the DMA controller If a conflict occurs between the CPU via the data memory controller the lower priority requester is held off until the higher priority requester completes all accesses to ...

Page 59: ...data memory controller Program memory modes including cache operation and bootload operation are discussed Topic Page 3 1 TMS320C6202 Program Memory Controller 3 2 3 2 Memory Mapped Operation 3 4 3 3 Cache Operation 3 5 3 4 Bootload Operation 3 6 3 5 TMS320C6202 Data Memory Controller 3 7 Chapter 3 ...

Page 60: ...ring with a DMA transfer with the other block of program memory Table 3 1 and Table 3 2 compare the internal memory and cache configurations available on the current TMS320C6000 devices Figure 3 1 shows a block diagram of the connections between the C6202 CPU PMEMC and memory blocks The addresses shown in Figure 3 1 are for operation in memory map mode 1 Table 3 1 TMS320C6201 C6701 C6202 Internal ...

Page 61: ...202 Program Memory Controller Block Diagram Program Data Program Address Control 256 Program memory controller PMEMC C62x CPU Program fetch DMA bus controller External memory interface 256 256 mapped 0000 0000h 0001 FFFFh Block 0 128K bytes cached or mapped Block 1 128K bytes 0002 0000h 0003 FFFFh ...

Page 62: ...mapped mode both the CPU and the DMA can access all locations in both blocks of RAM Any access outside of the address space that the internal RAM is mapped to is forwarded to the EMIF The DMA can only access one of the two blocks of RAM at a time The CPU and DMA can access the internal RAM without interference as long as each accesses a different block If the CPU and DMA attempt to access the same...

Page 63: ... block 0 while the cache is flushed continues without stalling The CPU is halted during a cache flush You must ensure that all DMA accesses to block 1 have completed before the cache is enabled Note If you change the operation mode of the PMEMC you should use the follow ing assembly routine to ensure correct operation of the PMEMC This routine enables the cache To change the PMEMC operation mode t...

Page 64: ...dentically to the C6201 revision 3 During ROM bootload a 64K byte block of data is transferred from the beginning of CE1 to memory at address 0 During HPI bootload the host can read or write any in ternal or external memory location including the entire internal program space ...

Page 65: ...ections between the C6202 CPU DMEMC and memory blocks Table 3 5 shows the memory range occupied by each block of internal data RAM Figure 3 2 TMS320C6202 Data Memory Controller Block Diagram Block 1 64K bytes 64K bytes Block 0 Bank 3 Bank 2 Bank 1 Bank 0 Bank 3 Bank 2 Bank 1 Bank 0 controller DMA bus controller bus Peripheral interface memory External 16 16 16 16 DMEMC Data memory controller 32 32...

Page 66: ...e internal program and data bus is a 4K byte cache designated L1P for the program cache and L1D for the data cache The second level memory is a 64K byte memory block that is shared by both the program and data memory buses designated L2 Topic Page 4 1 Overview 4 2 4 2 Internal Memory Control Registers 4 5 4 3 L1P Description 4 6 4 4 L1D Description 4 9 4 5 L2 Description 4 13 Chapter 4 ...

Page 67: ...McBSP 1 Host port interface HPI C6200B CPU Data path 2 B register file L2 S2 M2 D2 Data path 1 A register file L1 S1 M1 D1 Instruction fetch Instruction dispatch Instruction decode Control registers In circuit emulation Interrupt control Multichannel buffered serial port 0 McBSP 0 Table 4 1 TMS320C6211 C6711 Internal Memory Configurations Device CPU Internal Memory Architecture Total Memory Bytes ...

Page 68: ...dress LD2 load data ST2 store data DA2 address program address program data 256 128 128 C62x CPU Program fetch Data path A Data path B L2 cache controller RAM 64K Bytes 64 64 EDMA 32 32 32 32 64 64 data address data snoop address L1 data cache controller Cache RAM 4K bytes 256 data address 256 L1 program cache controller Cache RAM 4K Bytes snoop address ...

Page 69: ...2 store data DA2 address program address program data 256 128 128 C67x CPU Program fetch Data path A Data path B L2 cache controller RAM 64K bytes 64 64 EDMA 32 64 32 64 64 64 data address data snoop address L1 data cache controller Cache RAM 4K bytes 256 data address 256 L1 program cache controller Cache RAM 4K bytes snoop address ...

Page 70: ...nt register 0184 4020h L1PFBAR L1P flush base address register 0184 4024h L1PFWC L1P flush word count register 0184 4030h L1DFBAR L1D flush base address register 0184 4034h L1DFWC L1D flush word count register 0184 5000h L2FLUSH L2 flush register 0184 5004h L2CLEAN L2 clean register 0184 8200h MAR0 Memory attribute register Region 0 0184 8204h MAR1 Memory attribute register Region 1 0184 8208h MAR...

Page 71: ...ta to the CPU in a single cycle Unlike the TMS320C6201 the L1P only operates as a cache and cannot be memory mapped The L1P does not support freeze or bypass modes The only values allowed for the program cache control PCC field in the CPU control and sta tus register CSR are 000b and 010b All other values for PCC are reserved as shown in Table 4 4 Table 4 4 Level 1 Program Cache Mode Settings Cach...

Page 72: ...data in the L1P Writ ing a 1 to the IP bit of the cache configuration register CCFG invalidates all of the cache tags in the L1P tag RAM This is a write only bit a read of this bit will always return a 0 Any CPU access to the L1P while invalidation is being processed stalls the CPU until the invalidation has completed and the CPU re quest has been fetched Figure 4 12 shows the format for the CCFG ...

Page 73: ...e from L1PFBAR to L1PFBAR L1PFWC 4 If L1PFBAR or L1PFWC are not aligned to the L1P line size 16 words all lines which contain any address in the specified range are invalidated Using this block invalida tion will not stall any pending CPU accesses The block invalidation begins when the L1PFWC is written therefore you should take care to ensure that the L1PFBAR register is set up correctly prior to...

Page 74: ...2 to fetch the data When the data is returned from the L2 the L1D analyzes the set that the addressed data maps to in each way The L1D controller stores the new data into the set that was least recently used LRU If the data in that set has been modified but the corresponding address has not be updated the cache line is dirty that data is written out to the L2 In this way cached data that has been ...

Page 75: ... 2 way cache Other Reserved Any initial load of an address causes a cache miss to occur The data is loaded and stored in the internal cache memory Any subsequent read from a cached address will cause a cache hit and that data will be loaded from the internal cache memory Figure 4 9 illustrates the organization for a 2 way set associa tive cache ...

Page 76: ...vel Internal Memory Figure 4 9 L1D 2 Way Set Associative Cache Diagram Tag Set Offset Word Subline L2 Data Data 1 0 32 64 256 0 1 Way 1 Tag RAM Address Data out Cache data Address Data out Way 0 Tag RAM Address Data out Cache data Address Data out ...

Page 77: ...BAR L1DFWC 4 The data in these lines is sent to the L2 to be stored in the original memory location In this way the L2 and external memory will remain coherent with the data that is invalidated If L1DFBAR or L1DFWC are not aligned to the L1D line size 8 words all lines which contain data in the address range specified are invalidated However only those words that are contained in the range from L1...

Page 78: ...bes the operation of this register Figure 4 12 Cache Configuration Register Fields CCFG 31 30 10 9 8 7 3 2 0 P rsvd IP ID rsvd L2MODE RW 0 R x W 0 W 0 R 0 0000 RW 000 Table 4 6 Cache Configuration Register Field Description Field Description L2MODE L2 Operation Mode L2MODE 000b 64K bytes SRAM L2MODE 001b 16K bytes 1 way cache 48 Kbytes mapped RAM L2MODE 010b 32K bytes 2 way cache 32 Kbytes mapped ...

Page 79: ...he L2 cache RAM is a function of the L2 Mode Each 16K byte block of RAM included in the cache adds one way to the associativity The line size for the L2 cache is 128 bytes Figure 4 13 shows the cache associativity for each L2 Mode Figure 4 13 L2 Memory Configuration 16K bytes 16K bytes 16K bytes ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 16K bytes 0000 0000h 0000 C000h 0000 8000h 0000 ...

Page 80: ... cause a bank collision and there fore a stall Concurrent accesses between the L1D and EDMA busses to differ ent banks can be serviced without stalling The priority bit P in the Cache Configuration Register CCFG determines the priority when a bank collision occurs between requestors If the P bit is set to 0 CPU accesses L1P and L1D are given priority over an EDMA request Thus any pending CPU reque...

Page 81: ...curs as follows The L2 first polls the L1D to determine if the evicted address is also cached in the L1D This is referred to as snooping the L1D If data is returned from the L1D it is written out to the EDMA Then both the L1D and L2 lines are invalidated If the L1D does not cache the evicted address the data in the L2 to written out to the EDMA In this case only the L2 line is invalidated Finally ...

Page 82: ...ta in L2 Fetch data from EDMA Yes No Fetch data from L2 Determine LRU location Is replaced data in L1D Write replaced data from L2 to EDMA No Write replaced data from L1D to EDMA Invalidate L1D line Invalidate L2 line Yes Store data to L2 Send data to CPU Done CPU requests data Is valid data in LRU location No Yes ...

Page 83: ...ange is cached by the L2 At reset the MAR registers are set to 0 To begin caching data in the L2 you must initialize the appropriate MAR register to 1 The MAR registers define cacheability for the EMIF only Addresses accessed by the EMIF which are not defined by the MAR registers are always cacheable Figure 4 15 shows the format for the MARs Table 4 3 illustrates which ad dress range each MAR bit ...

Page 84: ...ion Register Fields Continued MAR6 31 1 0 rsvd CE 1 2 R x RW 0 MAR7 31 1 0 rsvd CE 1 3 R x RW 0 MAR8 31 1 0 rsvd CE 2 0 R x RW 0 MAR9 31 1 0 rsvd CE 2 1 R x RW 0 MAR10 31 1 0 rsvd CE 2 2 R x RW 0 MAR11 31 1 0 rsvd CE 2 3 R x RW 0 MAR12 31 1 0 rsvd CE 3 0 R x RW 0 MAR12 31 1 0 rsvd CE 3 1 R x RW 0 ...

Page 85: ...0h B3FF FFFFh CE3 14 B200 0000h B2FF FFFFh CE3 13 B100 0000h B1FF FFFFh CE3 12 B000 0000h B0FF FFFFh CE3 11 A300 0000h A3FF FFFFh CE2 10 A200 0000h A2FF FFFFh CE2 9 A100 0000h A1FF FFFFh CE2 8 A000 0000h A0FF FFFFh CE2 7 9300 0000h 93FF FFFFh CE1 6 9200 0000h 92FF FFFFh CE1 5 9100 0000h 91FF FFFFh CE1 4 9000 0000h 90FF FFFFh CE1 3 8300 0000h 83FF FFFFh CE0 2 8200 0000h 82FF FFFFh CE0 1 8100 0000h ...

Page 86: ...ta will be fetched from the L2 on the next CPU request of that data 4 5 4 L2 Invalidation The method for user controlled invalidation of data in the L2 is similar to those for the L1P and the L1D For the L2 however there are two types of invalida tion The first type of invalidation is an L2 flush During a flush the contents of the L2 are copied out through the enhanced DMA Like an EDMA read or L2 ...

Page 87: ...ds to be flushed is equal to the value written into the L2FWC register The L2 controller then searches all L2 cache blocks for all lines whose external memory address falls within the range from L2FBAR to L2FBAR L2FWC 4 and copies that data through the EDMA to the external memory space The L1D is snooped to ensure that the correct data is stored in the original memory location The L2 flush occurs ...

Page 88: ...pending CPU accesses The clean begins when the L2CWC is written therefore you should take care to ensure that the L2CBAR register is set up correctly prior to writing the L2CWC If L2CBAR or L2CWC are not aligned to the L2 line size 32 words all lines which contain the words specified are inval idated However only those words that are contained in the range from L2CBAR to L2CBAR L2CWC 4 are saved t...

Page 89: ...ers 5 5 5 3 Memory Map 5 12 5 4 Initiating a Block Transfer 5 13 5 5 Transfer Counting 5 16 5 6 Synchronization Triggering DMA Transfers 5 17 5 7 Address Generation 5 22 5 8 Split Channel Operation 5 28 5 9 Resource Arbitration and Priority Configuration 5 30 5 10 DMA Channel Condition Determination 5 33 5 11 DMA Controller Structure 5 35 5 12 DMA Action Complete Pins 5 38 5 13 Emulation 5 38 Chap...

Page 90: ...as an independently programmable number of elements per frame In completing a frame transfer the DMA controller moves all elements in a single frame Block transfer Each DMA channel also has an independently program mable number of frames per block In completing a block transfer the DMA controller moves all frames that it has been programmed to move Transmit element transfer In split mode data elem...

Page 91: ... an in dex for the last transfer in a frame distinct from that used for the preceding transfers See section 5 7 1 on page 5 22 for more information Full 32 bit address range The DMA controller can access any region in the memory map J On chip data memory J On chip program memory when it is mapped into memory space rather than being used as cache J On chip peripherals J External memory via the EMIF...

Page 92: ...emory Mapped Modules DMA control Program memory cache Program memory controller EMIF PLL Host port DMA controller Peripheral bus controller EMIF control HPI control McBSPs Interrupt selector Timers Data memory Data memory controller CPU core 2 Data path 1 Data path Instruction decode Instruction dispatch Program fetch down Power Boot configuration Expansion bus ...

Page 93: ...A registers configure the operation of the DMA controller Table 5 1 and Table 5 2 show how the DMA control registers are mapped in memory These registers include the DMA global data count reload index and address registers as well as independent control registers for each channel ...

Page 94: ...84 002C DMA global count reload register B 5 5 0184 0030 DMA global index register A 5 7 2 0184 0034 DMA global index register B 5 7 2 0184 0038 DMA global address register A 5 8 0184 003C DMA global address register B 5 8 0184 0040 DMA channel 1 primary control 5 2 1 0184 0044 DMA channel 3 primary control 5 2 1 0184 0048 DMA channel 1 secondary control 5 10 0184 004C DMA channel 3 secondary cont...

Page 95: ...er 0184 0060 5 5 DMA channel 2 destination address 0184 001C 5 7 DMA channel 2 primary control 0184 0004 5 2 1 DMA channel 2 secondary control 0184 000C 5 10 DMA channel 2 source address 01840014 5 7 DMA channel 2 transfer counter 0184 0024 5 5 DMA channel 3 destination address 0184 005C 5 7 DMA channel 3 primary control 0184 0044 5 2 1 DMA channel 3 secondary control 0184 004C 5 10 DMA channel 3 ...

Page 96: ...ST RELOAD SRC RELOAD Source destination address reload for autoinitialization SRC DST RELOAD 00b do not reload during autoinitialization SRC DST RELOAD 01b use DMA global address register B as reload SRC DST RELOAD 10b use DMA global address register C as reload SRC DST RELOAD 11b use DMA global address register D as reload 5 4 1 1 EMOD Emulation mode EMOD 0 DMA channel keeps running during an emu...

Page 97: ...ter A as split address SPLIT 10b split channel mode enabled use DMA global address register B as split address SPLIT 11b split channel mode enabled use DMA global address register C as split address 5 8 ESIZE Element size ESIZE 00b 32 bit ESIZE 01b 16 bit ESIZE 10b 8 bit ESIZE 11b reserved 5 7 3 DST DIR SRC DIR Source destination address modification after element transfers SRC DST DIR 00b no modi...

Page 98: ... that the condition is not detected A1 value indicates that the condition is detected 5 10 SX IE FRAME IE LAST IE BLOCK IE RDROP IE WDROP IE DMA condition interrupt enable IE 0 associated condition does not enable DMA channel interrupt IE 1 associated condition enables DMA channel interrupt 5 10 1 RSYNC STAT WSYNC STAT Read or write synchronization status STAT 0 synchronization is not received STA...

Page 99: ... RW 0 RW 0 RW 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSYNC CLR WSYNC STAT RSYNC CLR RSYNC STAT WDROP IE WDROP COND RDROP IE RDROP COND BLOCK IE BLOCK COND LAST IE LAST COND FRAME IE FRAME COND SX IE SX COND RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Table 5 5 Synchronization Configuration Options Field Description Section WSPOL RSPOL Synchronization event po...

Page 100: ...set and Memory Maps Requests are sent to one of five re sources Expansion bus External memory interface Internal program memory Internal peripheral bus Internal data memory The source address is assumed to point to one of these four spaces throughout a block transfer This constraint also applies to the destination address ...

Page 101: ...e paused the value on STATUS becomes 10b after the DMA has completed all pending write transfers Stop operation The DMA controller can be stopped by writing START 00b Stop operation is identical to pause operation Once a DMA transfer is com pleted unless autoinitialization is enabled the DMA channel returns to the stopped state and STATUS becomes 00b after the DMA has completed all pending write t...

Page 102: ...toin itialization mode This capability allows a register to maintain its value during a block transfer Thus you do not have to dedicate a DMA global data register to a value that was static during a block transfer A single channel can use the same value for multiple channel registers For example in split channel mode the source and destination address can be the same On the other hand multi ple ch...

Page 103: ... to last frame in the current block transfer it completed Otherwise the new reload values would affect subsequent frame boundaries in the current block transfer However if the frame size is the same for the current and next block transfers this restriction is not relevant See section 5 5 for more explanation of the DMA channel transfer counter ...

Page 104: ...d sets the number of elements per frame This counter is decremented after the read transfer of each element The maximum number of elements per frame transfer is 65535 Once the last element in each frame is reached ELEMENT COUNT is re loaded with the 16 LSBs of the DMA controller global count reload register se lected by the CNT RELOAD field in the DMA controller channel primary control register Th...

Page 105: ...te in split mode SPLIT 0 00b RSYNC and WSYNC must be set to non zero values Up to 31 events are available If the value of these fields is set to 00000b no synchroniza tion is necessary In this case the read write or frame transfers occur as soon as the resource is available to that channel The association between values in these fields and events is shown in Table 5 6 This is similar to the fields...

Page 106: ...atched by each DMA channel The occurrence of this transition causes the asso ciated STAT field to be set in the DMA channel secondary control register If no synchronization is selected the STAT bit is always read as 1 A single event can trigger multiple actions User Clearing and Setting of Events By clearing pending events before starting a block transfer you can force the DMA channel to wait for ...

Page 107: ...onization is cleared when the DMA completes the request for the associated write transfer Clearing frame synchronization condition Frame synchronization clears the RSYNC STAT field when the DMA completes the request for the first read transfer in the new frame 5 6 3 Synchronization Control The DMA of the C6202 allows for more flexible control over how external synchronization events are recognized...

Page 108: ... a DMA sync event 6 The new DMA sync event triggers another burst Figure 5 7 Synchronization Flags Read burst 5 3 1 6 4 2 EXT_INTx active low EXT_INTx active high DMA frame In progress DMA sync event The new synchronization modes are available to better interface to an external FIFO that is serving as a data buffer Since a synchronization event is often triggered off of a flag indicating the amoun...

Page 109: ...nly occur during a burst For example if the C6202 is the reader from a FIFO the only way for the FIFO to go from half full HF active to less than half full HF inactive is by reading from the FIFO If the flag were to stay active throughout the burst then it is known that the data source was able to provide another set of data to the FIFO before the C6202 was able to read the frame These new feature...

Page 110: ...nd write transfer respectively Figure 5 8 DMA Channel Source Address Register 31 0 SOURCE ADDRESS RW x Figure 5 9 DMA Channel Destination Address Register 31 0 DESTINATION ADDRESS RW x 5 7 1 Basic Address Adjustment As indicated in Table 5 3 the SRC DIR and DST DIR fields can set the index to increment by element size decrement by element size use a global index value or not affect the DMA channel...

Page 111: ...E INDEX ELEMENT INDEX RW 0 RW 0 These fields affect address adjustment as follows ELEMENT INDEX For element transfers except the last one in a frame ELEMENT INDEX determines the amount to be added to the DMA channel source or the destination address register as selected by the SRC DIR or DST DIR field after each read or write transfer respectively FRAME INDEX If the read or write transfer is the l...

Page 112: ...dress If un aligned values are loaded operation is undefined There is no alignment restric tion for byte transfers All accesses to program memory must be 32 bits in width Also you must be aware of the endianness when trying to read a particular 8 bit or 16 bit field within a 32 bit register For example in little endian mode an ad dress ending in 00b selects the least significant byte whereas 11b s...

Page 113: ...oduct of ELE MENT COUNT and FRAME COUNT can form a larger effective element count The following must be performed If the address is to be adjusted using a programmable value DIR 11b FRAME INDEX must equal ELEMENT INDEX if the address adjustment is determined by a DMA global index register This applies to both source and destination addresses If the address is not to be adjusted by a program mable ...

Page 114: ...onsider a transfer with three frames F 3 of four halfword elements each E 4 S 2 This corresponds to ELEMENT INDEX 3 2 6 and FRAME INDEX 4 1 3 1 2 FFF0h Assume that the source address is not modified and the destination increments starting at 8000 0000h Table 5 7 shows the data in the order in which it is trans ferred and Table 5 8 shows how the data appears in memory after trans fers are finished ...

Page 115: ...Controller Table 5 8 Sorting in Order of First by Address Address Hex Frame Element 8000 0000 0 0 8000 0002 1 0 8000 0004 2 0 8000 0006 0 1 8000 0008 1 1 8000 000A 2 1 8000 000C 0 2 8000 000E 1 2 8000 0010 2 2 8000 0012 0 3 8000 0014 1 3 8000 0016 2 3 ...

Page 116: ...d transfer is written to the split destination address This event is synchronized as indicated by the WSYNC field The DMA channel keeps track internally of the num ber of pending receive transfers Receive element transfer J Receive read transfer Data is read from the split source address This event is synchronized as indicated by the RSYNC field J Receive write transfer Data from the receive read ...

Page 117: ...ains this information as internal status 5 8 2 Split Address Generation The DMA global address register selected by the SPLIT field in the DMA pri mary control register determines the address of the peripheral that is to be ac cessed for split transfer Split source address This address is the source for the input stream to the C6000 The selected DMA global address register contains this split sour...

Page 118: ... The AUXPRI field in the DMA auxiliary control register allows the same feature for the auxiliary channel When in high priority mode the associated channel s requests are sent to the appropriate resource with a signal indicating the high priority status By default all these fields are 0 dis abling the high priority mode Each resource can use this signal in its own priority scheme for resolving con...

Page 119: ... in the DMA auxiliary control register By default CH PRI contains the value 0000b at reset This value sets the auxiliary channel as highest priority followed by channel 0 followed by channel 1 followed by channel 2 with channel 3 having lowest priority Arbitration between channels occurs independently every CPU clock cycle for read and write transfers Any channel that is in the process of waiting ...

Page 120: ... stopped 5 9 2 Switching Channels A higher priority channel gains control of the DMA controller from a lower priority channel once it has received the necessary read synchronization In switching channels the current channel allows all data from requested reads to be com pleted The DMA controller determines which higher priority channel gains control of the DMA controller read operation That channe...

Page 121: ...atched by the CPU The SX COND WDROP COND and RDROP COND bits in the DMA channel secondary control register are treated as warning conditions If these conditions are enabled and active they move the DMA channel from the running to the pause state regardless of the value of the TCINT bit If a condition bit s associated IE bit is set that condition bit can be cleared only by you writing a 0 to it Oth...

Page 122: ...ared By Bitfield Event Occurs if If IE Enabled Otherwise SX Split transmit overrun receive The split operation is enabled and transmit element transfers get seven or more element transfers ahead of receive ele ment transfers A user write of 0 to COND FRAME Frame complete After the last write transfer in each frame is written to memory A user write of 0 to COND Two CPU clocks later LAST Last frame ...

Page 123: ...ead ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á EMIF read Á Á Á Á Á Burst FIFO Á Á ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á AUX Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CH2 holding Á Á Á CH3 holding Á CH1 holding Á Á Á Á Á Á Á ÁÁ ÁÁ ÁÁ ÁÁ Á Á CH0 holding 5 11 1 Read and Write Buses Each DMA channel can independently select one of four sources and destinations EMIF Internal program memory Internal data memory Internal peripheral bus Read and write bu...

Page 124: ...channel requests control of the DMA controller from a lower priority channel only the last request of the previous channel must finish After that the higher priority channel completes its requests through its holding registers The holding regis ters do not allow as high of a throughput through the DMA controller The lower priority channel begins no more read transfers but flushes the FIFO by compl...

Page 125: ...ime the DMA controller can have pending read transfer requests whose data has not yet arrived Once enough requests to fill the empty spots in the FIFO are out standing the DMA controller stops making further read transfer requests 5 11 3 Internal Holding Registers Each channel has dedicated internal holding registers If a DMA channel is transferring data through its holding registers rather than t...

Page 126: ...l purpose output If the DMAC pin reflects RSYNC STAT or WSYNC STAT externally then once a syn chronization event has been recognized DMAC transitions from low to high Once that event has been serviced as indicated by the status bit being cleared DMAC changes from high to low Before being sent off chip the DMAC signals are synchronized by CLKOUT1 The active period of these signals is a minimum of t...

Page 127: ...ocessing and EDMA Control Registers 6 6 6 4 Event Encoder 6 8 6 5 Parameter RAM PaRAM 6 9 6 6 EDMA Transfer Parameters 6 13 6 7 Initiating an EDMA Transfer 6 17 6 8 Types of EDMA Transfers 6 20 6 9 Linking EDMA Transfers 6 25 6 10 Element Size and Alignment 6 27 6 11 Element and Frame Array Count Updates 6 28 6 12 Src Dst Address Updates 6 29 6 13 EDMA Interrupt Generation 6 32 6 14 Resource Arbit...

Page 128: ...ty and the ability to link data transfers The EDMA allows movement of data to from internal memory L2 SRAM peripherals and between external memory spaces Figure 6 1 TMS320C6211 C6711 Block Diagram Data path 2 External memory interface EMIF Multi channel buffered serial port 1 McBSP 1 Multi channel buffered serial port 0 McBSP 0 Host port interface HPI Power down logic Enhanced DMA controller Timer...

Page 129: ...e A block diagram of the EDMA controller is shown in Figure 6 2 Figure 6 2 EDMA Controller encoder Event to EMIF peripherals FSM Address Generation scratch area Unused params Reload channel 15 params Reload channel 1 params Reload channel 0 Channel 15 params Channel 1 params Channel 0 params Events serial ports FIFO AF AE external devices EDMA parameter RAM ...

Page 130: ... stored in the EDMA parameter RAM are passed onto the address generation hardware which address the EMIF and or peripherals to perform the necessary read and write transactions The quick DMA QDMA is a new feature in the C6211 C6711 device that pro vides a fast and efficient way to transfer data QDMA functions similarly to the EDMA QDMA is best suited for applications that require quick data transf...

Page 131: ...s in an array cannot be spaced by an element index An array can be transferred with or without a synchronizing event The term array is used in context with 2 Dimensional transfers 2D transfer is defined below Block A group of arrays or frames form a block Synchronized and unsyn chronized block transfers are supported 2 dimensional 2D transfer A group of arrays comprise a 2D block transfer The firs...

Page 132: ...status register 6 14 01A0 FFE4h CIPR Channel interrupt pending register 6 13 01A0 FFE8h CIER Channel interrupt enable register 6 13 01A0 FFECh CCER Channel chain enable register 6 13 2 01A0 FFF0h ER Event register 6 3 01A0 FFF4h EER Event enable register 6 3 01A0 FFF8h ECR Event clear register 6 3 01A0 FFFCh ESR Event set register 6 3 In addition to the event register the EDMA controller also prov...

Page 133: ...also set events by way of the event set register ESR shown in Figure 6 6 Writing a 1 to one of the 16 event bits causes the corresponding bit to be set in the event register The event does not have to be enabled in this case This provides a good debugging tool and also allows the CPU to submit EDMA requests in the system Note that such CPU initiated EDMA transfers are basically unsynchronized tran...

Page 134: ... 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 6 4 Event Encoder Up to 16 events can be captured by the EDMA controller s event register Hence it is quite possible that events occur simultaneously on the EDMA event inputs For such cases the order of processing is resolved by the event encoder This mechanism only sorts simultaneous events and has nothing to do with the actual priori...

Page 135: ...d from one of the top 16 en tries in the PaRAM as shown in Table 6 2 These parameters are then sent to the address generation hardware The contents of the 2K byte parameter RAM shown in Table 6 2 comprises 16 transfer parameter entries for the 16 EDMA events Each entry is six words or 24 bytes totaling 384 bytes Address range is 01A0 0000h to 01A0 017Fh 69 transfer parameter sets that can be used ...

Page 136: ...eters for event 1 6 words 01A0 0030h to 01A0 0047h Parameters for event 2 6 words 01A0 0048h to 01A0 005Fh Parameters for event 3 6 words 01A0 0060h to 01A0 0077h Parameters for event 4 6 words 01A0 0078h to 01A0 008Fh Parameters for event 5 6 words 01A0 0090h to 01A0 00A7h Parameters for event 6 6 words 01A0 00A8h to 01A0 00BFh Parameters for event 7 6 words 01A0 00C0h to 01A0 00D7h Parameters fo...

Page 137: ...rds 01A0 0168h to 01A0 017Ch Parameters for event 15 6 words Address Reload Link Parameters 01A0 0180h Event N options 01A0 0184h Event N SRC address 01A0 0188h Event N array frame count Event N element count 01A0 018Ch Event N DST address 01A0 0190h Event N array frame index Event N element index 01A0 0194h Event N element count reload Event N link address 01A0 07E0h to 01A0 07F7h Reload paramete...

Page 138: ...shown in Figure 6 7 Access to the EDMA parameter RAM is provided only via the 32 bit peripheral bus Figure 6 7 Parameter Storage for an EDMA Event 31 16 15 0 Options Word 0 SRC Address Word 1 Array frame count FC Element count EC Word 2 DST address Word 3 Array frame index FIX Element index EIX Word 4 Element count reload ECRLD Link address Word 5 ...

Page 139: ...UM TCINT TCC rsvd LINK FS RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R 0 RW 0 RW 0 Table 6 3 EDMA Channel Options Field Description Field Description Section FS Frame synchronization FS 0 Frame sync is not needed to start a frame transfer FS 1 Frame synchronization enabled The relevant event for a given EDMA channel is used to synchronize a frame 6 7 LINK Linking events LINK 0 Linking of event parame...

Page 140: ...ends on 2DD 2DS and FS bit fields DUM SUM 10b Address decrement depends on 2DD 2DS and FS bit fields DUM SUM 11b Address modified by the element index frame index depending on 2DD 2DS and FS bits 6 12 ESIZE Element size ESIZE 00b 32 bit word ESIZE 01b 16 bit half word ESIZE 10b 8 bit byte ESIZE 11b reserved 6 10 PRI Priority levels for EDMA events PRI 000b Reserved Urgent priority level reserved O...

Page 141: ...element and frame index fields are used for address modification These fields are used by the EDMA for address updates depending on the type of transfer chosen 1D or 2D FS and SUM DUM fields The src dst address is modified by an index whose range is be tween 32768 and 32767 Element index provides an address offset to the next element in a frame Ele ment index is used only for non 2D transfers This...

Page 142: ...ddress in the parameter RAM from which the EDMA loads reloads the parameters of the next event in the chain Since the entire EDMA parameter RAM is located in the 01A0 xxxxh area only the lower 16 bit address matters The reload parameters are specified in the address range 01A0 0180h to 01A0 07F7h It is the user s responsibility to ensure that the link address is on a 24 byte boundary Operation is ...

Page 143: ...t triggered EDMA As the name suggests an event that is latched in the event register ER via the event encoder see section 6 4 causes its transfer parameters to be passed on to the address generation hard ware which performs the requested accesses Although the event causes this transfer it is very important that the event itself be enabled by the CPU Writing a 1 to the corresponding bit in EER enab...

Page 144: ...ts EDMA Channel Number Event Acronym Event Description 0 DSPINT Host port host to DSP interrupt 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INT EMIF SDRAM timer interrupt 4 EXT_INT4 External interrupt pin 4 5 EXT_INT5 External interrupt pin 5 6 EXT_INT6 External interrupt pin 6 7 EXT_INT7 External interrupt pin 7 8 EDMA_TCC8 EDMA transfer complete code 1000b interrupt 9 EDMA_TCC9 EDMA...

Page 145: ...ecific for a given EDMA channel In the case of 2 D transfers this EDMA channel R WSYNC event is used to transfer an array from the source to the destination Frame block synchronization FS 1 Setting FS 1 in the options field of an EDMA channel s transfer parameters causes the channel s frame transfers to be synchronized as per the event shown in Table 6 4 For the case of non 2D transfers each frame...

Page 146: ...oncept of a non 2D EDMA transfer with n elements in each frame and frame count is 2 for a total of three frames Each element in a frame is transferred from its source to destination address upon receiving the channel specific sync event After the channel receives a sync event it sends off a transfer request for DMA service The EDMA controller then decrements the element count EC by 1 in the parame...

Page 147: ... bit in options field should be set to 1 to enable frame synchronized transfer User specified element index EIX can be used to stagger elements in a frame Frame index FIX can be added to the start element address in a frame to de rive the next frame start address The address modification and count modifi cation depends on the type of update modes chosen They are mentioned here only for an understa...

Page 148: ...ck 6 8 2 1 R WSYNC 2D Transfer FS 0 A conceptual diagram in Figure 6 11 shows a 2 dimensional read write syn chronized transfer without frame synchronization Since this 2 D transfer is not frame synchronized the R WSYNC is the sync event on which every array or contiguous group of elements is transferred The example shows n elements in an array and number of arrays to be transferred as 3 frame cou...

Page 149: ...S 0 R WSYNC FS 0 FIX FIX 6 8 2 2 Frame Synchronized 2D Transfer FS 1 An example 2 dimensional block transfer with frame sync is shown in Figure 6 12 Again the contiguous group of elements element index EIX 0 form an array and the group of arrays form a 2D block frame Figure 6 12 Frame Synchronized 2 D Transfer First dimension Array 0 R WSYNC FS 1 EC 1 FIX E0 E2 E4 En E1 E3 E5 Second dimension E0 E...

Page 150: ...X is added to the last element address in an array to derive the next array start address This address update is trans parent to the user and does not reflect in the parameter RAM If linking is enabled LINK 1 the next EDMA block transfer in the link as spe cified by the link address is performed as soon as the next frame sync arrives ...

Page 151: ...ire EDMA parameter RAM is located in the 01A0 xxxxh area Therefore the 16 bit link address which corresponds to the lower 16 bit physical address is sufficient to specify the location of the next transfer entry The link address must be aligned on a 24 byte boundary An example of a linked EDMA transfer is shown in Figure 6 13 Figure 6 13 Linked EDMA Transfer Event N parameters Reload parameters at ...

Page 152: ...o limit to the length of linked transfers However the last transfer parameter entry should have its LINK 0 so that the linked transfer stops after the last transfer Table 6 5 Link Conditions LINK 1 Non 2D Transfers 2D Transfers Read write sync FS 0 Frame count 0 Element count 1 Frame count 0 Frame sync FS 1 Frame count 0 Always Once the link conditions are met for an event the transfer parameters ...

Page 153: ...ement size that the EDMA should use for a transfer The EDMA controller can transfer 32 bit words 16 bit half words or 8 bit bytes in a trans fer The addresses must be aligned on the element size boundary Word and half word accesses must be aligned on a word multiple of 4 and half word multi ple of 2 boundary respectively Unaligned values can result in undefined op eration ...

Page 154: ... if element count 1 Read write FS 0 2D 2DS 2DD 1 None 1 Frame FS 1 Non 2D 2DS 2DD 0 None 1 Frame FS 1 2D 2DS 2DD 1 None None No frame array count update occurs if the frame array count is zero FC 0 6 11 1 Element Count Reload ECRLD There is a special condition for reloading the element count for read write syn chronized FS 0 non 2D transfers In this case the address is updated by element size or e...

Page 155: ...e of the source or destination address depends on the transfer type chosen for both the source and destination For example a transfer from non 2D source to a 2D destination requires that the source be updated on a frame basis not on element basis to provide 2D type data to the destination Table 6 7 shows the amount by which the source address is modified for each of the combinations of FS 2DD 2DS ...

Page 156: ...e are in increasing order FIX Add signed FIX to the first element in a frame Element addresses in a frame are in decreasing order Reserved 11 None FIX Add signed FIX to the first element in a frame Element addresses in a frame are in increasing order FIX Add signed FIX to the first element in a frame Element addresses in a frame are in decreasing order Reserved FS 1 00 None EC x ESIZE bytes Add EC...

Page 157: ...ent size to the start address of previous frame EC x ESIZE bytes Subtract EC scaled by element size from the start address of previous frame Reserved 11 None FIX Add signed FIX to the first element in a frame Element addresses in a frame are in increasing order FIX Add signed FIX to the first element in a frame Element addresses in a frame are in decreasing order Reserved FS 1 00 None EC x ESIZE b...

Page 158: ...herefore for a channel completion event to generate an interrupt to the CPU the TCINT and the relevant CIER bit should be enabled CIPR is equivalent to an interrupt pending register whose sources are the transfer complete codes and CIER is similar to an interrupt enable register Note that if the CIER bit is disabled the channel completion event is still registered in the CIPR if its TCINT 1 Once t...

Page 159: ...b for any EDMA channel In other words there need not necessarily be a direct relation between the channel number and the TCC value This allows multiple channels having the same TCC value to cause the CPU to execute the same ISR for different channels Table 6 9 Transfer Complete Code TCC to DMA Interrupt Mapping TCC in Options TCINT 1 CIPR 15 0 Bits Set 0000b CIPR 0 0001b CIPR 1 0010b CIPR 2 0011b ...

Page 160: ... user specified 4 bit transfer complete codes TCC values 8 9 10 and 11 can be used to trigger another EDMA channel transfer The purpose of these events triggering an EDMA transfer is to provide the user the ability to chain several EDMA channels from one event that is driven by a peripheral or external device see Table 6 4 To enable the EDMA controller to chain channels by way of a single event th...

Page 161: ...ansfer Once channel 4 transfer is complete the EDMA controller initiates TCINT 1 the next transfer specified by EDMA channel 8 This is because TCC 1000b channel 4 transfer completion code is the sync event for EDMA channel 8 The corresponding CIPR bit 8 is set after channel 4 completes and generates an EDMA_INT provided CIER 8 1 to the CPU If the CPU interrupt is not desired the corresponding inte...

Page 162: ...the system by not submitting all requests in high priority Oversubscribing requests in one priority level can cause EDMA stalls This can be alleviated by balanced bandwidth distribution in the two levels of priority The requesters in the C6211 C6711 device include the L2 controller the EDMA and the HPI The HPI and L2 controller have direct ties to the address generation hardware so no EDMA paramet...

Page 163: ...PQ0 bit is used to ensure that all cache requests via L2 are completed before updating any memory windows for the emulation halt Another use is to determine the right time to do a task switch For example allocating L2 SRAM to a new task after ensuring that there are no EDMA transfer requests in progress which might write to L2 SRAM Lastly the PQ bits in PQSR can be used to allocate or submit reque...

Page 164: ...e QDMA is ideally suited 6 16 1 QDMA Registers The QDMA is supported through two sets of memory mapped registers The first set of five memory mapped registers contains parameters that define a QDMA transfer similar to the EDMA transfer parameters The second set of five memory mapped registers is a pseudo mapping of the registers in the first set The pseudo mapping registers optimize the QDMA perfo...

Page 165: ...g element count reload or transfer event linking Since the QDMA does not support transfer event linking bit 1 of the QDMA_OPT register is reserved as opposed to the LINK bit field in the EDMA options parameter Figure 6 20 QDMA Options Register QDMA_OPT QDMA_S_OPT 31 29 28 27 26 25 24 23 22 21 20 19 16 15 1 0 PRI ESIZE 2DS SUM 2DD DUM TCINT TCC Reserved FS RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R ...

Page 166: ...3 Pseudo Mappings The five physical QDMA registers are shadowed by five pseudo mappings of the same registers The pseudo mappings serve as the mechanism for actual ly submitting the transfer request for DMA service Writes to the physical QDMA registers i e addresses 0200 0000h 0200 0010h are performed as normal store operations A write to any one of the pseudo registers will per form a write to th...

Page 167: ...cause the QDMA and the L2 cache controller share the same transfer re quest node cache activity requiring the use of this transfer request node may delay submission of the QDMA transfer request The L2 controller is given priority during this sort of arbitration as in general it is assumed the cache re quests have a greater likelihood of eventually stalling the CPU The L2 write buffer typically kee...

Page 168: ...rnal processors use to access the memory space The host port control registers and signals are de scribed Topic Page 7 1 Overview 7 2 7 2 HPI Signal Descriptions 7 7 7 3 HPI Registers 7 16 7 4 Host Access Sequences 7 19 7 5 Memory Access Through the HPI During Reset 7 27 Chapter 7 ...

Page 169: ...uxiliary channel which connects the HPI to the CPU s memory space Both the host and the CPU can access the HPI control register HPIC The host can access the HPI address register HPIA the HPI data register HPID and the HPIC by using the external data and interface control signals Figure 7 1 shows the host port components in the block diagram of the on chip peripherals Figure 7 1 TMS320C6201 C6701 B...

Page 170: ...n hardware handles the read write requests and accesses Figure 7 2 TMS320C6211 C6711 Block Diagram Data path 2 External memory interface EMIF Multichannel buffered serial port 1 McBSP 1 Multichannel buffered serial port 0 McBSP 0 Host port interface HPI Power down logic Enhanced DMA controller Timer 1 Timer 0 L1P controller L1P cache direct mapped 4K bytes L1 S1 M1 D1 D2 M2 S2 L2 A register file D...

Page 171: ...e enables select the bytes to be written For HPIA HPIC and HPID read accesses the byte enables are not used The dedicated HHWIL pin indi cates whether the first or second halfword is being transferred An internal control register bit determines whether the first or second halfword is placed into the most significant halfword of a word For a full word access the host must not break the first halfwo...

Page 172: ...e or no additional logic The HPI can easily interface to hosts with a multiplexed or dedicated address data bus a data strobe and a read write strobe or two separate strobes for read and write The HCNTL 1 0 control inputs indicate which HPI register is accessed Using these inputs the host can specify an access to the HPIA which serves as the pointer into the source or destination space HPIC or HPI...

Page 173: ... attempts to access the host port before any previous HPID write access or prefetched HPID read access finishes In this case the HPI simply holds off the host via HRDY HRDY provides a convenient way to automatically adjust the host access rate to the rate of data delivery from the DMA auxiliary channel no software handshake is needed In the cases of hardware systems that cannot take advantage of t...

Page 174: ...nables Data write byte enables HR W I 1 Read write strobe address line or multiplexed address data Read write select HCS I 1 Address or control lines Data strobe inputs HDS 1 2 I 1 1 Read strobe and write strobe or data strobe Data strobe inputs HRDY O 1 Asynchronous ready Ready status of current HPI access HINT O 1 Host interrupt input Interrupt signal to host I input O output Z high impedance 7 ...

Page 175: ...r in this chapter determines which halfword is least sig nificant or most significant HHWIL is low for the first halfword and high for the second halfword Since byte enable pins are removed from the C6211 C6711 HPI HHWIL in combination with HWOB specify the half word position in the data register HPID This is shown in Table 7 3 along with the LSB address bits depending on endianness Table 7 3 HPI ...

Page 176: ...s the most significant byte in the halfword Table 7 4 lists the valid combinations of byte enables For byte writes only one HBE in either of the halfword accesses can be enabled For halfword data writes both the HBEs must be held active low in either but not both halfword access For word accesses both HBEs must be held active low in both half word accesses No other combinations are valid The selec...

Page 177: ... and low to write HPI A host without either a read write select output or a read or write strobe can use an address line for this function 7 2 6 Ready HRDY When active low HRDY indicates that the HPI is ready for a transfer to be performed When inactive HRDY indicates that the HPI is busy completing the internal portion of a current read access or a previous HPID read prefetch or write access HCS ...

Page 178: ...ite strobes connect these strobes to either HDS1 or HDS2 Hosts with a single data strobe connect it to either HDS1 or a HDS2 tying the unused pin high Regardless of HDS1 and HDS2 connec tions HR W is required to determine the direction of transfer Because HDS1 and HDS2 are internally exclusive NORed hosts with a high true data strobe can connect this strobe to either HDS1 or HDS2 with the other si...

Page 179: ...t 7 2 10 HPI Bus Access Figure 7 6 and Figure 7 8 show HPI access timing for cases in which HAS is not used Figure 7 7 and Figure 7 9 show HPI access timing for cases in which HAS is used HSTROBE represents the internally generated strobe described in Figure 7 5 Control signals HCNTL 1 0 HR W HHWIL and HBE 1 0 are typically driven by the host HCNTL 1 0 and HR W should have the same val ues for bot...

Page 180: ...second read access the data is already present in HPID the DMA auxiliary channel performs word reads Thus the second halfword HPID read never encounters a not ready condition and HRDY remains low In the case of HPID read access with autoincrement the data pointed to by the next address is fetched immediately after the completion of the current read Therefore after the second halfword transfer of t...

Page 181: ...S Not Used Tied High HAS HCNTL 1 0 HR W HHWIL HSTROBE HCS 1st halfword HD 15 0 output HRDY case 1 HRDY case 2 2nd halfword Figure 7 7 HPI Read Timing HAS Used HAS HCNTL 1 0 HR W HHWIL HSTROBE 1st halfword HCS HD 15 0 output HRDY case 1 HRDY case 2 2nd halfword ...

Page 182: ...Figure 7 8 HPI Write Timing HAS Not Used Tied High HAS HCNTL 1 0 HR W HHWIL HSTROBE HCS HBE 1 0 1st halfword HRDY 2nd halfword HD 15 0 Figure 7 9 HPI Write Timing HAS Used HAS HCNTL 1 0 HR W HBE 1 0 HHWIL 1st halfword HRDY 2nd halfword HD 15 0 HSTROBE ...

Page 183: ...PI Registers Register Abbreviation Register Name Host Read Write Access CPU Read Write Access CPU Read Write Hex Byte Address HPID HPI data RW HPIA HPI address RW HPIC HPI control RW RW 0188 0000h 7 3 1 HPI Control Register HPIC The HPIC shown in Figure 7 10 and summarized in Table 7 6 is normally the first register accessed to set configuration bits and initialize the interface The HPIC is organi...

Page 184: ...nal to host Not masked by HCS as the HRDY pin is If HRDY 0 the internal bus is waiting for an HPI data access request to finish 7 3 2 FETCH Host fetch request The value read by the host or CPU from this register field is always 0 The host writes a 1 to this bit to request a fetch into HPID of the word at the address pointed to by HPIA The 1 is never actually written to this bit however 7 3 2 7 3 2...

Page 185: ...bits in the HPIC The DSPINT bit is tied directly to the internal DSPINT signal By writing DSPINT 1 when DSPINT 0 the host causes a low to high transition on the DSPINT signal If you program the selection of the DSPINT interrupt with inter rupt selector the transition of DSPINT is detected as an interrupt condition by the CPU The CPU can clear the DSPINT bits by writing a 1 to DSPINT Neither a host...

Page 186: ... HPI can begin this request The second halfword access always has HRDY active because all previous accesses have been completed for the first halfword access 7 4 1 Host Initialization of HPIC and HPIA Before accessing data the host must first initialize the HWOB bit of the HPIC register and then HPIA in this order because HWOB affects the HPIA access After initializing HWOB the host can write to H...

Page 187: ...rd at address 80001234h and that the word value at that location is 789ABCDEh Table 7 9 and Table 7 10 summarize this access for HWOB 1 and HWOB 0 respectively On the first halfword access the HPI waits for any previous requests to finish During this time HRDY pin is held high Then the HPI sends the read request to the DMA auxiliary channel If no pre vious requests are pending this read request oc...

Page 188: ...E Host reads 2nd halfword 789A xx 1 11 0 1 00090009 80001234 789ABCDE Note A in this table indicates the value is unknown Table 7 10 Data Read Access to HPI Without Autoincrement HWOB 0 Value During Access Value After Access Event HD HBE 1 0 HR W HCNTL 1 0 HRD Y HHWIL HPIC HPIA HPID Host reads HPID1st half word Data not ready xx 1 11 1 0 00000000 80001234 Host reads HPID 1st half word Data ready 7...

Page 189: ...le 7 11 summarizes a read access with autoincrement After the first half word access is complete with the rising edge of the first HSTROBE the ad dress increments to the next word or 80001238h in this example Assume that the data at that location is 87654321h This data is prefetched and loaded into HPID Prefetching begins on the rising edge of HSTROBE in the second half word read Table 7 11 Read A...

Page 190: ... by HWOB is over written by the data coming from the host and the first HBE 1 0 pair is latched while the HHWIL pin is low The second halfword portion of HPID is overwritten by the data coming from the host and the second HBE 1 0 pair is latched on the rising edge of HSTROBE while the HHWIL pin is high At the end of this write ac cess with the second rising edge of HSTROBE HPID is transferred as a...

Page 191: ...1 00010001 80001234 wxyz5566 00005566 Note A in this table indicates the value is unknown Table 7 14 Data Write Access to HPI Without Autoincrement HWOB 0 Value During Access Value After Access Location Event HD HBE 1 0 HR W HCNTL 1 0 HRDY HHWIL HPIC HPIA HPID Location 80001234 Host writes HPID 1st halfword Waiting for previous access to complete wxyz 11 0 11 1 0 00000000 80001234 00000000 Host wr...

Page 192: ...NTL 1 0 HRDY HHWIL HPIC HPIA HPID Location 80001234 Location 80001238 Host writes HPID 1st halfword Waiting for previous access to complete 5566 00 0 10 1 0 00010001 80001234 00000000 00000000 Host writes HPID 1st halfword Ready 5566 00 0 10 0 0 00090009 80001234 5566 00000000 00000000 Host writes HPID 2nd halfword wxyz 11 0 10 0 1 00090009 80001234 wxyz5566 00000000 00000000 Host writes HPID 1st ...

Page 193: ...10 0 0 00080008 80001238 33rs5566 00005566 00000000 Host writes HPID 2nd halfword nopq 11 0 10 0 1 00080008 80001238 33rsnopq 00005566 00000000 Waiting for access to complete 1 00000000 80001238 33rsnopq 00005566 33000000 wxyz rs and nopq represent don t care values on HPID Note A in this table indicates the value is unknown 7 4 6 Single Halfword Cycles In normal operation every transfer must cons...

Page 194: ... Write accesses are triggered by the second halfword access HHWIL word high Thus if the host desires to change only the portion of HPID selected by HHWIL high and the associated byte enables during con secutive write accesses only a single cycle is needed This technique s pri mary use is for memory fills the host writes both halfwords of the first write access with HBE 1 0 00 On subsequent write a...

Page 195: ...FIFOs and PCI interface chips Topic Page 8 1 Overview 8 2 8 2 Expansion Bus Signals 8 5 8 3 Expansion Bus Registers 8 6 8 4 Expansion Bus I O Port Operation 8 10 8 5 Expansion Bus Host Port Operation 8 22 8 6 Expansion Bus Arbitration 8 44 8 7 Boot Configuration Control via Expansion Bus 8 49 Chapter 8 ...

Page 196: ...sts must request the bus from the DSP For increased flexibility the internal arbiter can be disabled and the DSP requests the bus from an external arbiter The expansion bus has two major sub blocks the I O port and host port inter face A block diagram of the expansion bus is shown in Figure 8 1 Figure 8 1 Expansion Bus Block Diagram Expansion bus XCLKIN Expansion bus host channel XFCLK XD 31 0 XCE...

Page 197: ...ub block of the expansion bus consists of the host port interface This interface can operate in one of two modes synchronous and asynchro nous The synchronous mode offers master and slave functionality and has multiplexed address and data signals The asynchronous mode is slave only and is similar to the HPI on the C6201 C6211 C6701 C6711 but is extended to a 32 bit data path The asynchronous host ...

Page 198: ...ess controller DMA Timer 0 Timer 1 Program access cache controller Internal program memory 1 block program cache 1 block mapped program 128k bytes each 256k bytes total L1 S1 M1 D1 D2 M2 S2 L2 A register file Data path A B register file C6200B CPU Instruction fetch Instruction dispatch Instruction decode In circuit emulation Data access controller Internal data memory 128k bytes 2 blocks 4 blocks ...

Page 199: ...1 0 I O Z D 31 0 XFCLK O XFCLK XCLKIN I CLK XCE0 O CS O RE WE CS XCE1 O CS O RE WE CS XCE2 O CS O RE WE CS XCE3 O CS O RE WE CS XBE0 XA2 O Z XA2 O Z XA2 I O Z BE0 I BE0 XBE1 XA3 O Z XA3 O Z XA3 I O Z BE1 I BE1 XBE2 XA4 O Z XA4 O Z XA4 I O Z BE2 I BE2 XBE3 XA5 O Z XA5 O Z XA5 I O Z BE3 I BE3 XOE O OE O OE XRE O RE O RE XWE O WE O WE O WAIT XAS I O Z AS XRDY I XRDY I O Z READY O Z READY XW R I O Z W...

Page 200: ... Registers Byte Address Name 0188 0000 h Expansion Bus Global Control XBGC Register 0188 0004 h XCE1 Space Control Register 0188 0008 h XCE0 Space Control Register 0188 000c h Expansion Bus Host Port Interface Control XBHC Register 0188 0010 h XCE2 Space Control Register 0188 0014 h XCE3 Space Control Register 0188 0018 h Reserved 0188 001c h Reserved 0188 0020 h Expansion Bus Internal Master Addr...

Page 201: ...s access to the entire memory map of the DSP including memory mapped registers Table 8 3 summarizes the registers that the expansion bus host port uses for communication between the host device and the CPU Table 8 3 Expansion Bus Host Port Registers Register Abbreviation Register Name Host Read Write Access C6202 Read Write Access Memory Mapped Address XBHC Expansion Bus Host Port Control RW 0x018...

Page 202: ...spaces operating in FIFO mode FMOD 1 Glueless read FIFO interface If XCE3 is selected for FIFO mode then XOE acts as FIFO output enable and XCE3 acts as FIFO read enable XOE is disabled in all other XCE spaces regardless of MType setting XFCEN FIFO clock enable XFCEN 0 XFCLK held high XFCEN 1 XFCLK enabled to clock The FIFO clock enable cannot be changed while a DMA request to XCE space is active ...

Page 203: ... 1111 RW 111111 RW 11 RW 1111 R 00 RW 111111 R 0 R xx R 00 RW 11 Table 8 5 Expansion Bus XCE 0 1 2 3 Space Control Register Field Description Field Description MTYPE Others Memory type is configured during boot using pullup or pulldown resistors on the expansion bus MTYPE 010b 32 bit wide asynchronous interface MTYPE 101b 32 bit wide FIFO interface Reserved The remaining fields are defined in deta...

Page 204: ...can be set to a multiple of 4 ensure word strides thus incrementing to a different location after each frame has completed Although the expansion bus does not explicitly support memory widths of less than 32 bits the DMA can be used to read write to 8 bit or 16 bit peripherals or FIFOs by controlling the byte half word logical addressing For example if an 8 bit wide FIFO is in XCE2 then the DMA ES...

Page 205: ...terface to Four 8 Bit FIFOs Decoder XD 31 24 XD 23 16 XD 15 8 XD 7 0 XA 3 WEN CLK FIFO 3 D 7 0 OE REN FIFO 2 WEN REN CLK OE D 7 0 XA 2 XRE XCE XD 31 0 XOE XFCLK CLK D 7 0 OE FIFO 4 REN WEN XD 31 0 FIFO 1 REN WEN D 7 0 OE CLK Table 8 6 Addressing Scheme Case When Expansion Bus is Interfaced to Four 8 Bit FIFOs Logical Address A 31 6 A5 A4 A3 A2 A1 A0 FIFO 1 Address X X X 0 0 0 0 FIFO 2 Address X X ...

Page 206: ...1 0 Physical Address XA5 XA4 XA3 XA2 8 4 1 Asynchronous Mode The asynchronous cycles of the expansion bus are identical to the asynchronous cycles provided by the EMIF During asynchronous peripheral accesses XRDY acts as an active high ready input and XBE 3 0 XA 5 2 operate as address signals XA 5 2 The remaining asynchronous peripheral signals operate exactly like their EMIF counterpart For a com...

Page 207: ...n bus offers a glueless and or low glue interface to standard synchronous FIFOs The expansion bus can interface up to four write FIFOs without using glue logic one per XCE space or three write FIFOs and a single read FIFO in XCE3 only However with a minimal amount of glue up to 16 read and write FIFOs can be used per XCE space The XOE XRE XWE and XCEn signals are not tri stated while the DSP re le...

Page 208: ... a single write FIFO per XCE space Acts as read enable signal XCE3 only XWE O FIFO write enable Write enable signal for FIFO Must be logically OR ed with corresponding XCE signal to ensure that only one FIFO is addressed at a time XRE O FIFO read enable Read enable signal for FIFO Must be logically OR ed with corresponding XCE signal to ensure that only one FIFO is addressed at a time XOE O FIFO o...

Page 209: ...s true the XCE signal is tied directly to the write enable input of the FIFO If a read FIFO is also used in the same XCE space glue must be used since the XCE signal also goes low for reads from the read FIFO Figure 8 8 shows an interface to a read FIFO and a write FIFO in the same XCE space For this example the XCE signal is used to gate the appropriate read write strobes to the FIFOs The FIFO wr...

Page 210: ...E RCLK REN WCLK WEN FIFO Synchronous Q 31 0 FF EF HF Q 31 0 EXT_INTy D 31 0 WEN WCLK FIFO Synchronous Q 31 0 HF FF EF OE REN RCLK bus Expansion XD 31 0 EXT_INTx XWE XOE XRE XCEx XFCLK Figure 8 9 FIFO Write Cycles XA2 XA3 XA4 XA5 D2 D3 D4 D5 XFCLK XCEx XBE 3 0 XA 5 2 XWE WEN XCEx XWE XD 31 0 ...

Page 211: ...signal and XOE is used as the output enable signal of the FIFO Figure 8 10 shows this interface Figure 8 11 shows the timing diagram for this interface If the glueless read FIFO mode is not chosen then a minimal amount of glue can be used in any XCE space specified as a FIFO interface Figure 8 8 shows the required glue Figure 8 12 shows the timing diagram for the case when glue logic is used to re...

Page 212: ... has been written to The writer should not write to the FIFO until the offset registers have been programmed For programming or reading the offset registers back to back accesses must be done For example the first XFCLK edge with the program input to the FIFO low programs the PAE register and then the second XFCLK edge programs the PAF register Also for 9 bit or large 18 bit FIFOs it is common to ...

Page 213: ...cated FIFO interfaces the in terrupt signals EXT_INT4 EXT_INT5 EXT_INT6 and EXT_INT7 are used as flags to control DMA transfers The flag polarity used to start transfer can be programmed in the DMA secondary control register The CPU EXT_INT and DMA EXT_INT polarity are controlled separately For more details see the DMA section ...

Page 214: ... address and a non changing source address The source address does not change since the FIFO is located in a fixed memory location The content of relevant regis ters and DMA channel primary control register are shown in Table 8 9 and Table 8 10 Table 8 9 Content of Relevant Registers single frame transfer Register Contents DMA primary control register 0000 0041h DMA source 4000 0000h DMA destinati...

Page 215: ...ields are shown in Table 8 11 Table 8 12 and Table 8 13 Table 8 11 Content of Relevant Registers multiple frame transfer Register Content DMA Primary Control Register 0401 0041h DMA Secondary Control Register 0008 0000h DMA Source 4000 0000h DMA Destination 8000 0000h Transfer Counter Register 000A 0100h Global Counter Reload Register A 0000 0100h Table 8 12 Content of TMS320C6202 DMA Primary Cont...

Page 216: ...ronous host port mode en ables interfacing to genuine asynchronous devices The expansion bus host port block diagram is shown is Figure 8 13 Figure 8 13 Expansion Bus Host Port Interface Block Diagram XCS XCNTL XBOFF XBLAST XW R XAS XRDY XBE 3 0 XD 31 0 XHOLDA XHOLD C6202 block Control arbitration Bus MUX XBGC XBHC registers control host port Expansion bus bus peripheral controller memory Data lat...

Page 217: ...mory location in the DSP memory map being accessed by the external mastering data transactions This address is a 30 bit word address The two LSBbits in this register are used by the host to enable or disable autoincrement of XBISA register and to trigger the interrupt by setting the DSPINT bit The XBISA register is shown in Figure 8 15 and described in Table 8 14 Figure 8 15 Expansion Bus Internal...

Page 218: ...nous mode Figure 8 16 Expansion Bus Internal Master Address Register 31 0 XBIMA RW 0000 0000 0000 0000 0000 0000 0000 0000 8 5 1 4 Expansion Bus External Address Register This register is set by the C6202 when the DSP wants to initiate transfer on the expansion bus The content of the XBEA register shown in Figure 8 17 appears on the XD 31 0 lines during an address phase of the transfer initiated b...

Page 219: ...o wake up the DSP from reset is cleared when this bit is set START 1 0 Start bus master transaction Start 01 starts a write burst transaction from address pointed by XBIMA to address pointed by XBEA Start 10 starts a read burst transaction from address pointed by XBEA to address pointed by XBIMA Writing 00 to the the START field while an active transfer is stalled by XRDY high aborts the transfer ...

Page 220: ...on XCLKIN I 1 Clock Input Expansion bus clock maximum clock speed is 1 4 of the CPU clock speed XCS I 1 Chip Select Selects the C6202 as a target of an external master XHOLD I O Z 1 Hold Request Case 1 Internal bus arbiter enabled XHOLD is asserted by external device to request use of the expansion bus The C6202 asserts XHOLDA when control is granted Case 2 Internal bus arbiter disabled The C6202 ...

Page 221: ...gnal selects between XBD and XBISA register XCNTL 0 access is made to the XBD register XCNTL 1 access is made to the XBISA register XBE 3 0 XA 5 2 I O Z 4 Byte enables During host port accesses these signals operate as XBE 3 0 BE3 byte enable 3 XD 31 24 BE2 byte enable 2 XD 23 16 BE1 byte enable 1 XD 15 8 BE0 byte enable 0 XD 7 0 XW R I O Z 1 Read write Write read enable Polarity of this signal is...

Page 222: ...set to control the number of elements being transferred 4 The start field is written controlling whether the external access is a read or write burst An interrupt is generated at the completion of the transfer if specified by the INTSRC bit in the XBHC register Figure 8 19 and Figure 8 20 show examples of timing diagrams for a burst read and write when the C6202 is mastering the bus In this case i...

Page 223: ...output XBLAST output XBE 3 0 output XD 31 0 i o XRDY input XWAIT output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BE D1 D2 D3 D4 D5 D6 D7 D8 AD The step by step description of the events marked above the waveforms in Figure 8 19 follows 1 The C6202 requests the expansion bus by asserting XHOLD output 2 The DSP waits for the expansion bus 3 The external bus arbiter asserts the ...

Page 224: ...data D4 and XRDY stays asserted 16 The external device presents next data D5 and XRDY stays asserted The DSP can not accept the new data D5 and asserts XWAIT 17 The external device recognizes XWAIT and keeps the D5 on the expan sion bus The XRDY is asserted and indicates that the external device is ready waiting for the DSP to accept the data 18 The DSP deasserts XWAIT and accepts D5 19 The extern...

Page 225: ...19 XCLKIN input XHOLD output XHOLDA input XAS output XW R output XBLAST output XBE 3 0 output XD 31 0 i o XRDY input XWAIT output BE AD D1 D2 D3 D4 D5 D6 D7 D8 The step by step description of the events marked above the waveforms in Figure 8 20 follows 1 The DSP requests the expansion bus XHOLD asserted 2 The DSP waits for the XHOLDA signal to be asserted by the external arbi ter 3 The external bu...

Page 226: ...next data D4 The external device is ready to take D4 11 The DSP presents next data D5 The external device is ready to take D5 12 The DSP is not ready to present D6 and asserts XWAIT The external de vice is waiting for the DSP to present new data 13 Same as 12 14 Same as 12 15 The DSP presents next data D6 and negates XWAIT The external de vice is ready to take D6 16 The DSP presents next data D7 T...

Page 227: ...sting the expansion bus XHOLD 1 when the internal bus arbiter is enabled XARB 1 or 2 The DSP is the expansion bus master XHOLD 1 and XHOLDA 1 and the internal bus arbiter is disabled XARB 0 The backoff request is not serviced until all current master transfers are completed internally This allows read data to be flushed out of the pipeline The XBOFF signal is not recognized during I O port transfe...

Page 228: ...is still holding the expansion bus waiting for XRDY to become low 4 The external device asserts XBOFF indicating a potential deadlock condi tion 5 The DSP responds by releasing the expansion bus When the internal bus arbiter is enabled the DSP asserts XHOLDA When the internal bus arbi ter is disabled the DSP deasserts XHOLD It can take a several clock cycles before C6202 responds to XBOFF Figure 8...

Page 229: ...ister The data transfer can take place with or without auto incrementing the internal C6202 memory address register XBISA Whether the XBISA gets autoincremented is determined by the AINC bit field of the XBISA register To read write from the C6202 memory space the host must follow the following sequence 1 The host writes the transfer source destination address to the XBISA reg ister and sets AINC ...

Page 230: ...e C6x presents the data to the external host This is controlled via the XRDY output of the C6x If the XRDY signal is high this indicates to the external host that the C6x is not ready to receive data for a write or is not ready to present data for a read and is in the wait phase The data phase is entered when the C6x asserts XRDY signal indicating that read data should be latched by the external h...

Page 231: ...host and throttled by the XRDY signal Figure 8 22 The Expansion Bus Master Writes a Burst of Data to the TMS320C6202 9 D4 Wait 8 7 6 5 Ready 4 3 Wait 2 1 C6202 latches CNTL D3 D2 D1 XCLKIN XCS input XCNTL input XW R input XBE 3 0 input XBLAST input XAS input XD 31 0 XRDY output Write 0000 Word Internal src dst addr 0 XBD 1 XBISA Write The boot configuration for XBLAST and XW R BLPOL 0 and RWPOL 0 ...

Page 232: ... written to the XBISA register when the C202 asserts the XRDY output low 4 The XAS and XCNTL signals are both low and XCS is low indicating XBD register as the destination for the following transaction The XW R is high specifying that a write access is taking place 5 The expansion bus master presents the valid data The data is written to the XBD register on the rising edge of the XCLKIN when XRDY ...

Page 233: ... external host and throttled by the XRDY signal Figure 8 23 The Bus Master Reads a Burst of Data From the TMS320C6202 9 D4 Wait 8 7 6 5 Ready 4 3 Wait 2 1 C6202 latches CNTL D3 D2 D1 XCLKIN XCS input XCNTL input XW R input XBE 3 0 input XBLAST input XAS input XD XRDY output 0000 Word Internal src dst 0 XBD 1 XBISA Write Read The boot configuration for XBLAST and XRW BLPOL 0 and RWPOL 0 See Table 8...

Page 234: ...he external host A high XRDY indicates that the C6202 is not ready 3 The data is written to the XBISA register when the C6202 asserts the XRDY output low 4 The XAS and XCNTL signals are both low and XCS is low indicating XBD register as the destination for the following transaction The XW R is low specifying that a read access is taking place 5 The C6202 presents the valid data and drives XRDY low...

Page 235: ...yte Enables Functionality of these signals is the same as on the C6201 HPI during a read XBE do not matter During a write BE3 byte enable 3 XD 31 24 BE2 byte enable 2 XD 23 16 BE1 byte enable 1 XD 15 8 BE0 byte enable 0 XD 7 0 XCNTL I 1 Control Signal This signal selects between XBD and XBISA register XCNTL 0 access is made to the XBD register XCNTL 1 access is made to the XBISA register XW R I 1 ...

Page 236: ...fied by the XBISA register Read or write is dictated by the XW R signal The XBISA register is auto in cremented or not depending on what is written to the AINC bit during step 1 If the expansion bus host port is configured to operate in asynchronous mode the XCS signal is used for four purposes 3 To select the expansion bus host port as a target of an external master 4 On a read the falling edge o...

Page 237: ...iagrams for Asynchronous Host Port Mode of the Expansion Bus XCNTL input word word XR W input XCS input XRDY output XCNTL input XD 31 0 XBE 3 0 input XR W input XCS input XRDY output XD 31 0 XBE 3 0 input Asynchronous Host Port Write Timing Asynchronous Host Port Read Timing ...

Page 238: ...n frames if a DMA block transfer is in progress When the C6202 releases the expansion bus the host port signals become tristated except for the I O port signals XWE XWAIT XOE XRE XCE 3 0 and XFCLK which are not af fected 8 6 1 Internal Bus Arbiter Enabled In this mode the C6202 owns the expansion bus by default The C6202 wakes up from reset as the master of the expansion bus and all other devices ...

Page 239: ...bus should not be granted to the C6202 unless requested by XHOLD Figure 8 26 illustrates XHOLD and XHOLDA functionality in this mode Figure 8 26 Timing Diagrams for Bus Arbitration XHOLD XHOLDA Internal Bus Arbiter Disabled OUTPUTS XHOLD output XHOLDA input The C6202 is Master of the Bus When the internal bus arbiter is disabled XARB 0 and the expansion bus master transfer is initiated by writing ...

Page 240: ...e DSP waits for the host transfer to com plete and then asserts XHOLD N A Host transfer to the expansion bus in progress DMA request to ex pansion bus IO port and aux DMA re quests are pending After the DSP gets the expansion bus the pending aux iliary DMA request is executed first since for the ex pansion bus the aux DMA channel always has priority over the other DMA channels After the auxiliary ...

Page 241: ...s not drop the XHOLD be tween these two transfers Aux DMA request pending The DSP asserts the XHOLD and once it gets the ex pansion bus the transfer starts DMA transfer to ex pansion bus IO port in progress XBOFF is ignored if a DMA transfer to the expansion bus IO port is in progress YES N A Aux DMA transfer in progress The DSP releases ownership of the expansion bus as soon as possible After tha...

Page 242: ... For example if an unsynchronized DMA trans fer is set up to perform 4 frames of 32 elements each and an auxiliary transfer becomes pending either by an external host asserting the XHOLD request signal if the internal arbiter is enabled or by the C6202 attempting to begin a master transfer by writing to the start bits of the XBHC register internal arbiter enabled or disabled the auxiliary request ...

Page 243: ...iter to define expansion bus host port mode to define memory type used in each expansion bus memory space and to define FIFO mode All expansion data pins XD 31 0 should be configured by pull up pull down resistors Reserved fields should be pulled down Detailed description of boot configuration is shown in Figure 8 28 and Table 8 20 Figure 8 28 Expansion Bus Boot Configuration via Pull Up Pull Down...

Page 244: ...ve high HMOD Host mode status in XB HPIC HMOD 0 external host interface operates in asynchronous slave mode HMOD 1 external host interface is in synchronous master slave mode XARB Expansion bus arbiter status in XBGC XARB 0 Internal expansion bus arbiter is disabled XARB 1 Internal expansion bus arbiter is enabled FMOD FIFO mode status in XBGC FMOD 0 Glue is used for FIFO read interface in all XCE...

Page 245: ...ibed along with diagrams showing the connections between the EMIF and each supported memory type Topic Page 9 1 Overview 9 2 9 2 Resetting the EMIF 9 8 9 3 EMIF Registers 9 9 9 4 SDRAM Interface 9 20 9 5 SBSRAM Interface 9 43 9 6 Asynchronous Interface 9 49 9 7 Hold Interface 9 60 9 8 Memory Request Priority 9 61 9 9 Boundary Conditions When Writing to EMIF Registers 9 63 9 10 Clock Output Enablin...

Page 246: ...ices CPU program fetches The on chip data memory controller that services CPU data fetches The on chip DMA controller An external shared memory device controller If multiple requests arrive simultaneously the EMIF prioritizes them and performs the necessary number of operations A block diagram of the TMS320C6201 C6202 C6701 is shown in Figure 9 1 and the signals shown there are summarized in Table...

Page 247: ...gram fetch down Power Boot configuration Figure 9 2 External Memory Interface in the TMS320C6211 C6711BlockDiagram L1P cache direct mapped 4K bytes L2 memory 4 banks 64K bytes L1D cache 2 way set associative 4K bytes Timer 0 Timer 1 Enhanced DMA controller Power down logic External memory interface EMIF Multichannel buffered serial port 1 McBSP 1 Host port interface HPI CPU core Data path 2 B regi...

Page 248: ...M interface Asynchronous interfaces all external Shared by Program memory controller Data memory controller controller DMA EMIF interface memory External HOLDA HOLD SDCLK SDA10 SDWE SDCAS SDRAS SSCLK SSWE SSOE SSADS ARE AWE AOE ARDY BE 3 0 CE 3 0 EA 21 2 ED 31 0 CLKOUT2 CLKOUT1 Internal peripheral bus Control registers ...

Page 249: ...emories run off CLKOUT2 which is equal to 1 2x the CPU clock rate Figure 9 4 TMS320C6202 External Memory Interface CLKOUT ED 31 0 CE 3 0 BE 3 0 ARDY AOE ARE AWE SDRAS SSOE SDCAS SSADS SDWE SSWE EA 21 2 SDA10 Shared by all external interfaces Asynchronous interface Synchronous interface External memory interface EMIF Control registers Internal peripheral bus Data memory controller Program memory co...

Page 250: ...ed memory interfaces use a four word burst length which is optimized for the two level cache architecture The SDRAM interface is flexible allowing interfaces to a wide range of SDRAM configurations The SDA10 pin has been removed Address pin EA 12 serves the func tion of the SDA10 pin for the SDRAM memories Figure 9 5 TMS320C6211 C6711 External Memory Interface ED 31 0 CE 3 0 BE 3 0 ARDY AOE SDRAS ...

Page 251: ...om two LSBs of the byte address n n n n ARDY I Ready Active low asynchronous ready input used to insert wait states for slow memories and peripherals n n n M AOE O Z Active low output enable for asynchronous memory interface n n n M AWE O Z Active low write strobe for asynchronous memory interface n n n M ARE O Z Active low read strobe for asynchronous memory interface n n M M SSADS O Z Active low...

Page 252: ...els with the exception of the clock outputs SDCLK SSCLK CLKOUT1 and CLKOUT2 CLKOUT2 SSCLK and SDCLK are driven high or low during ac tive RESET CLKOUT1 continues clocking unless the values on the PLL con figuration pins are changed On the C6211 ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values ECLKOUT will continue to clock as long as ECLKIN is provi...

Page 253: ...rol 0180 0014h EMIF CE3 space control 0180 0018h EMIF SDRAM control 0180 001Ch EMIF SDRAM timing register 9 3 1 Global Control Register The EMIF global control register shown in Figure 9 6 and summarized in Table 9 3 configures parameters common to all the CE spaces Figure 9 6 EMIF Global Control Register Diagram 31 16 Reserved R 0000 0000 0000 0000 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsv Rsv...

Page 254: ...LKIN ECLKOUT SDCEN enables CLKOUT2 on the C6202 if SDRAM is used in the system specified by the MTYPE field in in the CE space control register SSCEN SSCLK enable SSCEN 0 SSCLK held high SSCEN 1 SSCLK enabled to clock There is no SSCLK on the C6211 C6711 All external memories run off of the EMIF external clock ECLKIN ECLKOUT SSCEN enables CLKOUT2 on the C6202 if SBSRAM is used in the system specif...

Page 255: ...eld exists only in C6211 C6711 Fields do not exist in C6211 C6711 Fields do not exist in C6202 The C6202 EMIF registers are similar to those of the C6201 Due to the combination of the SDRAM and SBSRAM signals the user cannot include both SDRAM and SBSRAM in the same system The EMIF global control register bitfields are modified slightly to reflect this change In order to support as many common pro...

Page 256: ...ne synchronous memory type is supported at a time If a CE space is set as a synchronous memory type SBSRAM or SDRAM all synchronous memory spaces are changed to the new memory type For example if CE2 is configured as SDRAM MTYPE 011b setting CE3 as SBSRAM MTYPE 100b changes CE2 and CE3 to SBSRAM Changing a CE space memory type to asynchronous memory does not affect the memory type of other CE spac...

Page 257: ...DRAM CE0 CE2 CE3 only MTYPE 100b 32 bit wide SBSRAM Memory type of the corresponding CE spaces for C6211 C6711 MTYPE 0000b 8 bit wide asynchronous interface previously ROM MTYPE 0001b 16 bit wide asynchronous interface previously ROM MTYPE 0010b 32 bit wide asynchronous interface MTYPE 0011b 32 bit wide SDRAM MTYPE 0100b 32 bit wide SBSRAM MTYPE 1000b 8 bit wide SDRAM MTYPE 1001b 16 bit wide SDRAM...

Page 258: ... regardless of the width of the device Ac cesses to 8 bit memories have logical address bit 0 output on EA 2 Packing and unpacking is automatically performed by the EMIF for word ac cesses to external memories of less than 32 bits For a 32 bit write to an 8 bit memory the data is automatically unpacked into bytes such that the bytes are written to byte address N N 1 N 2 then N 3 Likewise for 32 bi...

Page 259: ...tics The fields in this register are shown in Figure 9 10 and Figure 9 11 and described in Table 9 5 These registers should not be modified while accessing SDRAM Figure 9 10 TMS320C6201 C6202 C6701 EMIF SDRAM Control Register 31 28 27 26 25 24 23 20 19 16 Reserved Rsv SDWID RFEN INIT TRCD TRP RW 000 R 0 RW 0 RW 1 W 1 RW 1000 RW 1000 15 12 11 0 TRC Reserved RW 1111 R 0000 0000 0000 Figure 9 11 TMS3...

Page 260: ...AM refresh enabled SDWID SDRAM width select SDWID 0 Each external SDRAM space consists of four 8 bit SDRAMs SDWID 1 Each external SDRAM space consists of two 16 bit SDRAMs SDCSZ SDRAM column size SDCSZ 00 9 column address pins SDCSZ 01 8 column address pins SDCSZ 10 10 column address pins SDCSZ 11 reserved SDRSZ SDRAM column size SDCSZ 00 11 row address pins SDCSZ 01 12 row address pins SDCSZ 10 1...

Page 261: ...able 9 6 describe the fields of the SDRAM timing register The C6211 C6711 can control the number of refreshes performed when the refresh counter expires via the XRFR field Up to four refreshes can be per formed when the refresh counter expires Figure 9 12 EMIF SDRAM Timing Register 31 26 25 24 23 12 11 0 Reserved XRFR COUNTER PERIOD R 0000 00 R 0 RW 00 R 0000 1000 0000 R 0101 1101 1100 RW 0000 100...

Page 262: ...ations or speed characteristics Second the C6211 C6711 can maintain seamless data transfer from external SDRAM due to features like hidden precharge and multiple open banks Figure 9 13 shows the SDRAM extension register and Table 9 7 discusses these parameters Figure 9 13 TMS320C6211 C6711 SDRAM Extension Register 31 21 20 19 18 17 16 15 14 12 11 10 9 8 7 6 5 4 3 1 0 Rsvd WR2RD WR2DEAC WR2WR R2WDQ...

Page 263: ...UT cycles RD2RD 0 READ to READ 1 ECLKOUT cycle RD2RD 1 READ to READ 2 ECLKOUT cycle RD2DEAC Specifies number of cycles between READ to DEAC DCAB of the SDRAM in ECLKOUT cycles RD2DEAC of cycles READ to DEAC DCAB 1 RD2WR Specifies number of cycles between READ to WRITE command of the SDRAM in ECLKOUT cycles RD2WR of cycles READ to WRITE 1 R2WDQM Specifies number of of cycles that BEx signals must b...

Page 264: ...n the C6211 C6711 is able to open up to four pages of SDRAM simultaneously The pages can all be in a single CE space or distributed across multiple CE spaces Table 9 10 summa rizes the pin connection and related signals specific to SDRAM operation Table 9 8 does not apply to the C6211 C6711 because page characteristics are programmable The C6211 C6711 can interface to any SDRAM that has 8 to 10 co...

Page 265: ...F interface memory External ED 31 0 EA 11 2 SDA10 EA 13 BE 3 0 SDWE SDCAS SDRAS Clock CEn Clock SDCLK for C6201 C6701 Clock CLKOUT2 for C6202 Figure 9 15 TMS320C6211 C6711 EMIF to 16M Bit SDRAM Interface VCC 16M bit SDRAM D 31 0 A 9 0 A 10 A 11 DQM 3 0 CKE WE CAS RAS CLK CS EMIF interface memory External ED 31 0 EA 11 2 EA 12 EA 13 BE 3 0 SDWE SDCAS SDRAS ECLKOUT CEn External clock ECLKIN ...

Page 266: ...SDWE SDCAS SDRAS Clock CEn Clock SDCLK for C6201 C6701 Clock CLKOUT2 for C6202 Table 9 9 TMS320C6201 C6202 C6701 SDRAM Memory Population SDRAM Size SDRAM Banks SDRAM Width Devices per CE Space Memory Size per CE Space 16M bit 2 16 bits 2 4M bytes 16M bit 2 8 bits 4 8M bytes 64M bit 4 16 bits 2 16M bytes The C6211 C6711 is not limited to these configurations because of larger possible CE spaces and...

Page 267: ...utputs CE3 CE2 or CE0 CS Chip select and command enable CS must be active low for a command to be clocked into the SDRAM CS does not affect data input or output once a write or read has begun CE1 does not support SDRAM CKE CKE clock enable Tied high when interfaced to EMIF to enable clocking always CLKOUT2 CLK SDRAM clock input Runs at 1 2 the CPU clock rate Used for synchronous memory interface o...

Page 268: ...SDRAM Interface 9 24 faces Since the C6211 C6711 does not perform background refreshes all three memory types may be included in the same system ...

Page 269: ...ntroller monitors the active row of SDRAM so that row boundaries are not crossed during the course of an access To accomplish this monitoring the EMIF stores the address of the open page and performs compares against that address for subsequent accesses to the SDRAM bank For the C6201 C6202 C6701 this storage and comparison is performed independently for each CE space so that a single page can be ...

Page 270: ...r head and allows the interface to capitalize fully on address locality of memory accesses 9 4 3 SDRAM Refresh The RFEN bit in the SDRAM control register selects the SDRAM refresh mode of the EMIF A value of 0 in RFEN disables all EMIF refreshes and you must ensure that refreshes are implemented in an external device A value of 1 in RFEN enables the EMIF to perform refreshes of SDRAM Refresh comma...

Page 271: ...aces containing SDRAM During idle times on the SDRAM interface s if no request is pending from the EMIF the SDRAM interface performs REFR commands as long as the counter value is nonzero This feature reduces the likelihood of having to perform urgent refreshes during actual SDRAM accesses If SDRAM is present in multiple CE spaces this refresh occurs only if all interfaces are idle with invalid pag...

Page 272: ... C6211 C6711 9 4 4 Mode Register Set The C6201 C6202 C6701 EMIF automatically performs a DCAB command followed by an MRS command whenever the INIT field in the EMIF SDRAM control register is set INIT can be set by device reset or by a user write Like DCAB and REFR commands MRS commands are performed to all CE spaces configured as SDRAM through the MTYPE field Following a hold the external requeste...

Page 273: ...ommand Figure 9 18 TMS320C6201 C6202 C6701 Mode Register Value 13 12 11 10 9 8 7 EA15 EA14 EA13 SDA10 EA11 EA10 EA9 Rsvd Write burst length Rsvd 0000 0 00 6 5 4 3 2 1 0 EA8 EA7 EA6 EA5 EA4 EA3 EA2 Read latency S I Burst length 0 1 1 0 000 Table 9 11 TMS320C6201 C6202 C6701 Implied SDRAM Configuration by MRS Value Field Selection Write burst length 1 word Read latency 3 cycles Serial interleave bur...

Page 274: ...e 9 19 TMS320C6211 C6711 Mode Register Value 0032h 13 12 11 10 9 8 7 EA15 EA14 EA13 SDA10 EA11 EA10 EA9 Rsvd Write burst length Rsvd 0000 0 00 6 5 4 3 2 1 0 EA8 EA7 EA6 EA5 EA4 EA3 EA2 Read latency S I Burst length 0 1 1 0 010 Figure 9 20 TMS320C6211 C6711 Mode Register Value 0022h 13 12 11 10 9 8 7 EA15 EA14 EA13 SDA10 EA11 EA10 EA9 Rsvd Write burst length Rsvd 0000 0 00 6 5 4 3 2 1 0 EA8 EA7 EA6...

Page 275: ...31 External Memory Interface Figure 9 21 SDRAM Mode Register Set MRS Command MRS value Clock CEx BE 3 0 EA 15 2 SDA10 SDRAS SDCAS SDWE MRS Clock SDCLK for C6201 C6701 Clock CLKOUT2 for C6202 Clock ECLKOUT for C6211 C6711 ...

Page 276: ...e from occurring following a READ or WRT command The following factors apply to the address shifting process for the C6211 C6711 The address shift is controlled completely by the column size field SDCSZ and is unaffected by the bank and row size fields The bank and row size are used internally to determine whether a page is opened EA12 is connected directly to A10 signal instead of using a dedicat...

Page 277: ... 10 E A 11 E A 10 E A 9 E A 8 E A 7 E A 6 E A 5 E A 4 E A 3 E A 2 of column address bits DRAM Cmd A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 8 RAS 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CAS 24 23 22 21 20 19 18 9 8 7 6 5 4 3 2 9 RAS 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 CAS 25 24 23 22 21 20 10 9 8 7 6 5 4 3 2 10 RAS 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 C...

Page 278: ...ents Consult the SDRAM data sheet for information on the parameters that are appropriate for your particular SDRAM Table 9 15 TMS320C6201 C6202 C6701 SDRAM Timing Parameters Parameter Description Value in CLKOUT2 ECLKIN2 Cycles tRC REFR command to ACTV MRS or subsequent REFR command TRC 1 tRCD ACTV command to READ or WRT command TRCD 1 tRP DCAB command to ACTV MRS or REFR command TRP 1 tRAS ACTV c...

Page 279: ...rior to REFR and MRS On the C6201 C6202 C6701 a DCAB is issued when a page boundary is crossed During the DCAB command SDA10 is driven high to ensure that all SDRAM banks are deactivated Figure 9 22 shows the timing diagram for SDRAM deactivation Figure 9 22 SDRAM DCAB Deactivate all Banks Clock CEx BE 3 0 EA 15 2 SDA10 EA12 SDRAS SDCAS SDWE DCAB Clock SDCLK for C6201 C6701 Clock CLKOUT2 for C6202...

Page 280: ...ecified by the bank select signals When a page boundary is crossed the DEAC command is used to close the open page The C6211 C6711 still supports the DCAB command to close all pages prior to REFR and MRS commands Figure 9 23 TMS320C6211 C6711 SDRAM DEAC Deactivate Single Bank DEAC Bank ECLKOUT CE BE 3 0 EA 21 13 EA 11 2 ED 31 0 SDRAS SDWE SDCAS EA12 ...

Page 281: ... command of the C6201 C6202 C6701 an idle cycle is inserted to meet timing requirements If required the bank is then deactivated with a DCAB command and the EMIF can begin a new page access If no new access is pending or an access is pending to the same page the DCAB command is not performed until the page informa tion becomes valid The values on EA 15 13 during column accesses and execu tion of t...

Page 282: ...command If no additional ac cess are pending to the EMIF as in Figure 9 25 the read burst completes and the unneeded data is disregarded If accesses are pending the read burst can be interrupted with a new command READ WRT DEAC DCAB controlled by the SDRAM extension register If a new access is not pending the DCAB DEAC command is not performed until the page information becomes invalid Figure 9 25...

Page 283: ...t length is one word a new write command is issued each cycle to perform the three word burst Following the final write command the C6201 C6202 C6701 inserts an idle cycle to meet SDRAM timing requirements The bank is then deactivated with a DCAB command and the memory interface can begin a new page ac cess If no new access is pending the DCAB command is not performed until the page information be...

Page 284: ...via the byte enable signals On the C6211 C6711 idle cycles are inserted as controlled by the parameters of the SDRAM extension register fields WR2RD WR2DEAC WR2WR TWR The bank is then deactivated with a DEAC command for C6211 C6711 and the memory interface can begin a new page access If no new access is pending the DEAC command is not performed until the page information becomes inval id see secti...

Page 285: ...with an ACTV command and after a delay controlled by Trcd the first read burst begins to bank 0 Since a 4 word burst is done by default the C6211 C6711 takes advantage of the extra cycles by issuing an ACTV com mand to open bank 1 while the first read burst takes place When the first read burst is scheduled to end the read burst to bank 1 is issued such that the 3 cycle CAS latency forces data to ...

Page 286: ...page in bank 1 can be opened This allows the write to bank 1 to begin immediately after the write burst to bank 0 ends as shown in Figure 9 29 Figure 9 29 Seamless SDRAM Write R R BE 3 0 ACTV B0 Write B0 n ACTV B1 Write B1 m ECLKOUT CEx EA 21 13 EA 11 2 EA12 ED 31 0 SDRAS SDCAS B0 Trcd 3 BE0 B0 n B1 m 1 SDWE BE1 BE1 BE2 BE0 BE1 BE2 B0 B1 B1 R Cn R Cm B0 n 1 B0 n 2 B0 n 3 B1 m B1 m ...

Page 287: ...701 the ADV signal of the SBSRAM is pulled high This disables the internal burst advance counter of the SBSRAM This interface al lows bursting by strobing a new address into the SBSRAM on every cycle The C6211 C6711 interface takes advantage of the internal advance counter of the SBSRAM For this interface the ADV signal is pulled low so that every access to the SBSRAM from the C6211 C6711 is assum...

Page 288: ...C6202 C6701 SBSRAM Interface SBSRAM SSRAM BE 3 0 BE 3 0 VCC D 31 0 A N 0 WE ADV OE ADSC CLK CS EMIF interface memory External ED 31 0 EA N 2 2 SSWE SSOE SSADS Clock CEn VCC ADSP Clock SSCLK for C6201 C6701 Clock CLKOUT2 for C6202 Figure 9 31 TMS320C6211 C6711 SBSRAM interface SBSRAM D 31 0 A N 0 BE 3 0 WE OE ADV ADSC CLK CS ED 31 0 EA N 2 2 BE 3 0 AOE SDRAS SSOE ARE SDCAS SSADS CEx GND AWE SDWE SS...

Page 289: ...nimum The initial 2 cycle penalty occurs when the direction changes on the bus In general the first access of a burst sequence incurs a 2 cycle start up penalty 9 5 1 SBSRAM Reads Figure 9 32 shows a four word read of an SBSRAM for the C6201 C6202 C6701 Every access strobes a new address into the SBSRAM indicated by the SSADS strobe low The first access requires an initial start up penalty of two ...

Page 290: ...nt the internal burst counter from rolling over to 000b The burst is terminated by deasserting the CEn signal while SSADS is strobed low Figure 9 33 TMS320C6211 C6711 SBSRAM Six Word Read D5 D6 D3 D4 D2 D1 EA 4 2 100b EA 4 2 010b BE5 BE6 BE3 BE4 BE2 BE1 SSWE SSOE SSADS ED 31 0 ECLKOUT EA 21 2 BE 3 0 CE Á Á Á Á D6 latched D5 latched D4 latched D3 Read latched latched D2 latched Read D1 latched ...

Page 291: ...he SBSRAM The first access requires an initial start up pen alty of two cycles thereafter all accesses can occur in a single SSCLK cycle Figure 9 34 TMS320C6201 C6202 C6701 SBSRAM Four Word Write D3 D4 D2 D1 A3 A4 A2 A1 Write Write Write BE3 BE4 BE2 BE1 SSWE SSOE SSADS ED 31 0 Clock EA 21 2 BE 3 0 CEx Write Clock SSCLK for C6201 C6701 Clock CLKOUT2 for C6202 ...

Page 292: ... ad dress is strobed into SBSRAM on the fifth cycle to prevent the internal burst counter from rolling over to 000b Figure 9 35 TMS320C6211 C6711 SBSRAM Write EA 4 2 100b EA 4 2 000b D1 D2 BE1 D5 D6 D4 D3 Write BE3 BE4 BE2 SSWE SSOE SSADS ED 31 0 ECLKOUT EA 21 2 BE 3 0 CEx Write BE5 BE6 ...

Page 293: ...shows the C6211 C6711 interface to 16 bit asynchronous SRAM in big endian mode The only difference is that ED 31 16 pins are used instead of ED 15 0 The asynchronous interface signals on the C6211 C6711 are similar to the C6201 except that the signals have been combined with the SDRAM and SBSRAM memory interface It has also been enhanced to allow for longer read hold and write hold times and the 8...

Page 294: ...UB 1 0 LB 1 0 BE 3 0 D 31 0 A N 0 R W OE CS EMIF interface memory External ED 31 0 EA N 2 2 AWE AOE CEn VDD Figure 9 37 TMS320C6211 C6711 EMIF to 16 bit SRAM Big Endian ARDY ARE SRAM B 1 0 BE 3 2 D 15 0 A N 0 R W OE CS EMIF interface memory External ED 31 16 EA N 2 2 AWE AOE CEn VDD ECLKIN External clock ...

Page 295: ...F interface memory External ARE ED 7 0 EA N 2 2 AOE CE1 VDD Figure 9 39 EMIF to 16 Bit ROM Interface A N 0 ROM ARDY D 15 0 OE CS EMIF interface memory External ARE ED 15 0 EA N 2 2 AOE CE1 VDD Figure 9 40 EMIF to 32 Bit ROM Interface A N 0 ROM ARDY D 31 0 OE CS EMIF interface memory External ARE ED 31 0 EA N 2 2 AOE CE1 VDD ...

Page 296: ...for all possible asynchronous memory widths The EMIF always reads the lower addresses first and packs these into the LSbytes It packs subsequent accesses into the higher order bytes Thus the expected packing format in ROM is always little endian regardless of the value of the LENDIAN bit Table 9 19 Byte Address to EA Mapping for Asynchronous Memory Widths EA Line 22 21 20 19 18 17 16 15 14 13 12 1...

Page 297: ...ime between the beginning of a memory cycle CE low ad dress valid and the activation of the read or write strobe Strobe The time between the activation and deactivation of the read ARE or write strobe AWE Hold The time between the deactivation of the read or write strobe and the end of the cycle which can be either an address change or the deactivation of the CE signal For the C6201 C6202 C6701 th...

Page 298: ...led on the CLKOUT1 on the ECLKOUT rising edge con current with the beginning of the hold period the end of the strobe pe riod and just prior to the ARE low to high transition At the end of the hold period AOE becomes inactive as long as another read access to the same CE space is not scheduled for the next cycle For the C6201 C6202 C6701 CE stays active for seven minus the value of Read Hold cycle...

Page 299: ...ad Timing Example Setup Strobe Hold CE Hold CLKOUT1 ECLKOUT BE Address Read D CE CE BE 3 0 EA 21 2 ED 31 0 AOE ARE AWE ARDY 2 3 1 6 On the C6211 C6711 CE goes high immediately after the programmed hold period CLKOUT1 referenced for C6201 C6202 C6701 ECLKOUT reference for C6211 C6711 ...

Page 300: ... period J AWE becomes inactive At the end of the hold period J ED goes into the high impedance state only if another write access to the same CE space is not scheduled for the next cycle J CE becomes inactive only if another write access to the same CE space is not scheduled for the next cycle For the C6201 C6202 C6701 if no write accesses are scheduled for the next cycle and write hold is set to ...

Page 301: ...Á Á Á Á On the C6211 C6711 CE goes high immediately after the programmed hold period CLKOUT1 referenced for C6201 C6202 C6701 ECLKOUT reference for C6211 C6711 9 6 5 Ready Input In addition to programmable access shaping you can insert extra cycles into the strobe period by deactivating the ARDY input The ready input is internally synchronized to the CPU clock This synchronization allows an asynch...

Page 302: ...is extended by one CLKOUT1 cycle Thus to effectively use CE to gen erate ARDY inactive with external logic the minimum of SETUP and STROBE should be four The read cycle in Figure 9 43 illustrates ready operation for the C6201 C6202 C6701 Figure 9 43 TMS320C6201 C6202 C6701 Ready Operation Address BE CE hold Hold extended Strobe Programmed strobe Setup 6 1 2 5 Ready sampled 2 ARDY AWE ARE AOE ED 31...

Page 303: ...OUT cycle Read data is latched by the C6211 on the cycle that ARDY is sampled high The ARE signal goes high on the the following cycle Therefore the strobe period is visibly extended by three cycles in Figure 9 44 although data is latched by the C6211 after the sec ond cycle Figure 9 44 TMS320C6211 C6711 Ready Operation latched Data Ready sampled Hold 1 Strobe extended 3 Programmed strobe 4 Setup ...

Page 304: ...pedance state The external device can then drive the bus as required The EMIF places all outputs in the high impedance state with the exception of the clock out puts CLKOUT1 CLKOUT2 SDCLK and or SSCLK depending on the device If any memory spaces are configured for SDRAM these memory spaces are deactivated and refreshed before HOLDA is asserted to the external master BUSREQ Bus request output C6211...

Page 305: ... all issued requests of the previous requester are allowed to finish while the new requester starts making its requests If the arbitration bit of the EMIF global control register is set RBTR8 1 and if a higher priority requester needs the EMIF the higher priority requester does not gain control until the current controller relinquishes control or until eight word re quests have finished If the arb...

Page 306: ...C program memory controller PMC and EDMA transactions are processed by the EDMA Other requestors include the hold interface and internal EMIF operations including mode register set MRS and refresh REFR Table 9 21 TMS320C6211 C6711 EMIF Prioritization of Requests Priority Requestor Highest External hold Mode register set refresh EDMA DMC EDMA PMC Lowest EDMA DMA ...

Page 307: ...e control register while any external operation is in progress SDRAM type while SDRAM initialization is active Changing the state of NOHOLD in the configuration while HOLD is active at the pin Changing the RBTR8 in the EMIF global control register while multiple EMIF requests are pending Initiating an SDRAM INIT MRS while the HOLD input or the HOLDA out put is active J The EMIF global control regi...

Page 308: ...lt Operation The EMIF continues operating during emulation halts Emulator accesses through the EMIF can work differently than the way the actual device works dur ing EMIF accesses This discrepancy can cause start up penalties after a halt operation 9 12 Power Down In power down 2 mode refresh is enabled SSCLK CLKOUT1 and CLKOUT2 are held low during power down 2 and power down 3 modes In power down...

Page 309: ...des and device configuration used by the TMS320C6000 platform It also describes the available boot processes and explains how the device is reset Topic Page 10 1 Overview 10 2 10 2 Device Reset 10 2 10 3 Boot Configuration 10 3 10 4 Device Configuration 10 10 Chapter 10 ...

Page 310: ... there Selection of the boot process used to initialize the memory at address 0 before the CPU is released from reset 10 2 Device Reset The external device reset uses an active low signal RESET While RESET is low the device is held in reset and is initialized to the prescribed reset state All 3 state outputs are placed in the high impedance state and all other outputs are returned to their default...

Page 311: ...four 8 bit devices SDWID 0 None 00001 MAP 0 SDRAM two 16 bit devices SDWID 1 None 00010 MAP 0 32 bit asynchronous with default timing None 00011 MAP 0 1 2x rate SBSRAM None 00100 MAP 0 1x rate SBSRAM None 00101 MAP 1 Internal None 00110 MAP 0 External default values HPI 00111 MAP 1 Internal HPI 01000 MAP 0 SDRAM four 8 bit devices SDWID 0 8 bit ROM with default timings 01001 MAP 0 SDRAM two16 bit ...

Page 312: ...0 1x rate SBSRAM 32 bit ROM with default timings 11101 MAP 1 Internal 32 bit ROM with default timings 11110 Reserved 11111 Reserved The TMS320C6201 and C6701 devices latch their boot configuration setting at reset from dedicated BOOTMODE pins The TMS3206202 latches its boot configuration from five data lines of the ex pansion bus XD 4 0 The XD 4 0 lines directly map to BOOTMODE 4 0 and should be c...

Page 313: ... CE 0 External memory interface CE 0 0100 0000 013F FFFF 4M External memory interface CE 1 External memory interface CE 0 0140 0000 0140 FFFF 64K Internal program RAM External memory interface CE 1 0141 0000 017F FFFF 4M 64K Reserved External memory interface CE 1 0180 0000 0183 FFFF 256K Internal peripheral bus EMIF registers 0184 0000 0187 FFFF 256K Internal peripheral bus DMA controller registe...

Page 314: ...000 0183 FFFF 256K Internal peripheral bus EMIF registers 0184 0000 0187 FFFF 256K Internal peripheral bus DMA controller registers 0188 0000 018B FFFF 256K Internal peripheral bus expansion bus registers 018C 0000 018F FFFF 256K Internal peripheral bus McBSP 0 registers 0190 0000 0193 FFFF 256K Internal peripheral bus McBSP 1 registers 0194 0000 0197 FFFF 256K Internal peripheral bus timer 0 regi...

Page 315: ...sters 0184 0000 0187 FFFF 256K Internal configuration bus L2 control registers 0188 0000 018B FFFF 256K Internal configuration bus HPI register 018C 0000 018F FFFF 256K Internal configuration bus McBSP 0 registers 0190 0000 0193 FFFF 256K Internal configuration bus McBSP 1 registers 0194 0000 0197 FFFF 256K Internal configuration bus timer 0 registers 0198 0000 019B FFFF 256K Internal configuratio...

Page 316: ...ture is not available on the C6211 C6711 ROM boot process The program located in external ROM is copied to ad dress 0 by the DMA EDMA controller Although the boot process begins when the device is released from external reset this transfer occurs while the CPU is internally held in reset This boot process also lets you choose the width of the ROM In this case the EMIF automatically assembles con s...

Page 317: ...e The CPU then begins execution from address 0 The DSPINT condition is not latched by the CPU because it occurs while the CPU is still in reset Also DSPINT wakes the CPU from internal reset only if the HPI boot process is selected All memory may be written to and read by the host This allows for the host to verify what it sends to the proc essor if required Note The host interface used during host...

Page 318: ... to operate in either big or little endian mode Set the LENDIAN flag to 1 to select little endian and 0 to select big endian The selection method varies slightly among different devices The C6201 and C6701 have a dedicated LENDIAN input pin The C6211 and C6711 sample the ninth data line of the host port interface HD 8 The C6202 samples the ninth data line of the expansion bus XD 8 The device pin s...

Page 319: ... and timing diagrams for the McBSPs Topic Page 11 1 Features 11 2 11 2 McBSP Interface Signals and Registers 11 3 11 3 Data Transmission and Reception 11 18 11 4 µ LAW A LAW Companding Hardware Operation 11 50 11 5 Programmable Clock and Framing 11 53 11 6 Multichannel Selection Operation 11 68 11 7 SPI Protocol CLKSTP 11 80 11 8 McBSP Pins as General Purpose I O 11 87 Chapter 11 ...

Page 320: ...ffering capability through the 5 channel DMA controller In addition the McBSP has the following capabilities Direct interface to J T1 E1 framers J MVIP switching compatible and ST BUS compliant devices including H MVIP framers H H 100 framers H SCSA framers J IOM 2 compliant devices J AC97 compliant devices The necessary multi phase frame synchro nization capability is provided J IIS compliant dev...

Page 321: ...iagram ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á...

Page 322: ...nd the EDMA in the TMS320C6211 C6711 device can access the DRR and DXR in all the memory mapped locations shown in Table 11 3 A write to any location in 30000000h 33FFFFFFh is equivalent to a write to the DXR of McBSP 0 at 018C0004h A read from any location in 30000000h 3FFFFFFh is equivalent to a read from the DRR of McBSP 0 at 018C0000h Similarly a read from any location in 34000000h 3FFFFFFFh i...

Page 323: ...BSP Interface Signals Pin I O Z Description CLKR I O Z Receive clock CLKX I O Z Transmit clock CLKS I External clock DR I Received serial data DX O Z Transmitted serial data FSR I O Z Receive frame synchronization FSX I O Z Transmit frame synchronization Note I Input O Output Z High Impedance ...

Page 324: ...nel control register 11 6 1 018C 001C 0190 001C 01A4 001C RCER Receive channel enable register 11 6 3 1 018C 0020 0190 0020 01A4 0020 XCER Transmit channel enable register 11 6 3 1 018C 0024 0190 0024 01A4 0024 PCR Pin control register 11 2 1 The RBR RSR and XSR are not directly accessible via the CPU or the DMA controller The CPU and DMA controller can only read this register they cannot write to...

Page 325: ...Table 11 5 and Table 11 6 summarize the SPCR and the PCR fields respectively The PCR is also used to configure the serial port pins as general purpose in puts or outputs during receiver and or transmitter reset for more information see Section 11 8 Figure 11 2 Serial Port Control Register SPCR 31 24 23 22 21 20 19 18 17 16 reserved FRST GRST XINTM XSYNCERR XEMPTY XRDY XRST R 0 RW 0 RW 0 RW 0 RW 0 ...

Page 326: ...upt mode RINTM 00b RINT driven by RRDY RINTM 01b RINT generated by end of subframe in multichannel operation RINTM 10b RINT generated by a new frame synchronization RINTM 11b RINT generated by RSYNCERR 11 3 3 XINTM Transmit interrupt mode XINTM 00b XINT driven by XRDY XINTM 01b XINT generated by end of subframe in multichannel operation XINTM 10b XINT generated by a new frame synchronization XINTM...

Page 327: ...y for data to be written to DXR 11 3 2 RRST Receiver reset This resets or enables the receiver RRST 0 The serial port receiver is disabled and is in reset state RRST 1 The serial port receiver is enabled 11 3 1 XRST Transmitter reset This resets or enables the transmitter XRST 0 The serial port transmitter is disabled and is in reset state XRST 1 The serial port transmitter is enabled 11 3 1 DLB D...

Page 328: ... 0 Clock starts with rising edge without delay CLKSTP 10b and CLKXP 1 Clock starts with falling edge without delay CLKSTP 11b and CLKXP 0 Clock starts with rising edge with delay CLKSTP 11b and CLKXP 1 Clock starts with falling edge with delay 11 7 DXENA DX Enabler applicable only for the C6211 C6711 device Enable extra delay for DX turn on time This bit controls the Hi Z enable on the DX pin not ...

Page 329: ...OEN Transmitter in general purpose I O mode only when XRST 0 in SPCR XIOEN 0 CLKS pin is not a general purpose input DX pin is not a general purpose output FSX and CLKX are not general purpose I Os XIOEN 1 CLKS pin is a general purpose input DX pin is a general purpose output FSX and CLKX are general purpose I Os These serial port pins do not per form serial port operation 11 8 FSXM Transmit frame...

Page 330: ...he internal sample rate genera tor During SPI mode CLKSTP in SPCR is a nonzero value CLKXM 0 McBSP is a slave and CLKX is driven by the SPI master in the system CLKR is internally driven by CLKX CLKXM 1 McBSP is a master and generates the transmitter clock CLKX to drive its receiver clock CLKR and the shift clock of the SPI compliant slaves in the system 11 5 2 7 and 11 8 11 7 CLKS_STAT CLKS pin s...

Page 331: ...Continued Name Section Function CLKXP Transmit clock polarity CLKXP 0 Transmit data driven on rising edge of CLKX CLKXP 1 Transmit data driven on falling edge of CLKX 11 3 4 1 and 11 8 CLKRP Receive clock polarity CLKRP 0 Receive data sampled on falling edge of CLKR CLKRP 1 Receive data sampled on rising edge of CLKR 11 3 4 1 and 11 8 ...

Page 332: ...DLY RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 8 7 5 4 3 0 RPHASE 2 RFRLEN1 RWDLEN1 RWDREVRS Reserved RW 0 RW 0 RW 0 RW 0 R 0 R X PHASE 2 feature s available only on C6211 C6711 RWDREVRS and XWDREVRS 32 bit reversal feature is applicable only to the C6211 C6711 device Figure 11 5 Transmit Control Register XCR 31 30 24 23 21 20 19 18 17 16 XPHASE XFRLEN2 XWDLEN2 XCOMPAND XFIG XDATDLY RW 0 RW 0 RW 0 RW 0 R...

Page 333: ...in phase 1 and phase 2 RFRLEN 1 2 000 0000b 1 word per phase RFRLEN 1 2 000 0001b 2 words per phase S S S RFRLEN 1 2 111 1111b 128 words per phase 11 3 4 4 XFRLEN 1 2 Transmit frame length in phase 1 and phase 2 XFRLEN 1 2 000 0000b 1 word per phase XFRLEN 1 2 000 0001b 2 words per phase S S S XFRLEN 1 2 111 1111b 128 words per phase 11 3 4 4 RWDLEN 1 2 Receive element length in phase 1 and phase ...

Page 334: ... first RCOMPAND 10b Compand using µ law for receive data RCOMPAND 11b Compand using A law for receive data 11 4 XCOMPAND Transmit companding mode Modes other than 00b are only applicable when the appropriate XWDLEN is 000b indicating 8 bit data XCOMPAND 00b No companding Data transfer starts with MSB first XCOMPAND 01b No companding 8 bit data Transfer starts with LSB first XCOMPAND 10b Compand us...

Page 335: ... This is applicable when frame syncs are inputs or outputs 11 3 4 3 XPHASE 2 Transmit PHASE 2 Applicable only for dual phase frames Mainly used for I2S feature Applicable only for C6211 C6711 device XPHASE 2 0 The start of phase 2 is unaffected by transmit frame sync XPHASE 2 1 The second phase in a dual phase frame starts when the transmit frame sync transitions to the opposite edge that started ...

Page 336: ...e in the DXR is copied to the XSR Otherwise the DXR is copied to the XSR when the last bit of data is shifted out on the DX After transmit frame synchronization the XSR begins shifting out the transmit data on the DX 11 3 1 Resetting the Serial Port R X RST GRST and RESET The serial port can be reset in the following two ways Device reset RESET pin is low places the receiver the transmitter and th...

Page 337: ...s bits RFULL RRDY and RSYNCERR and the transmit status bits XEMPTY XRDY and XSYNCERR Device reset When the McBSP is reset due to device reset the entire se rial port including the transmitter receiver and the sample rate generator is reset All input only pins and 3 state pins should be in a known state The output only pin DX is in the high impedance state Since the sample rate generator is also re...

Page 338: ...enerator reset As mentioned previously the sample rate generator is reset when the device is reset or when its reset bit GRST is written with 0 In the case of device reset the CLKG signal is driven by a divide by 2 internal clock source and FSG is driven inactive low The in ternal clock source for the C6211 C6711 is CPU clock while the internal clock source for C6211 C6711 is CPU 2 clock half of t...

Page 339: ...ould be loaded by the CPU or DMA only when the transmitter is not in reset XRST 1 The exception to this rule occurs during non digital loop back mode which is described in sec tion 11 4 1 3 The multichannel selection registers MCR XCER and RCER can be modified at any time as long as they are not being used by the current block in the multichannel selection See section 11 6 3 2 for more infor matio...

Page 340: ...synchronization event to the DMA controller via XEVT Also the transmit interrupt XINT to the CPU can be driven by XRDY if XINTM 00b default value in the SPCR 11 3 3 CPU Interrupts R X INT The receive interrupt RINT and transmit interrupt XINT signal the CPU of changes to the serial port status Four options exist for configuring these inter rupts These options are set by the receive transmit interr...

Page 341: ...ame synchronization to first data bit which can be 0 1 or 2 bit delays Right or left justification as well as sign extension or zero filling for receive data The configuration can be independent for receive and transmit Figure 11 6 Frame and Clock Operation D R X FS R X CLK R X B3 B2 B1 B0 B5 B4 B6 B7 A0 A1 ÁÁ ÁÁ ÁÁ ÁÁ Á Á 11 3 4 1 Frame and Clock Operation Receive and transmit frame sync pulses c...

Page 342: ...h sync signals are inverted if the polarity bit FS R X P 1 before being sent to the FS R X pin Figure 11 37 shows this in version using XOR gates On the transmit side the transmit clock polarity bit CLKXP sets the edge used to shift and clock out transmit data Data is always transmitted on the rising edge of CLKX_int If CLKXP 1 and external clocking is selected CLKXM 0 and CLKX is an input the ext...

Page 343: ... element can be independently selected for each phase via R X FRLEN 1 2 and R X WDLEN 1 2 respectively Figure 11 8 shows a frame in which the first phase consists of two elements of 12 bits each followed by a second phase of three elements of 8 bits each The entire bit stream in the frame is contiguous no gaps exist either between elements or phases Table 11 9 shows the fields in the receive trans...

Page 344: ...y of devices does support some IIS for mats The start of second phase can be controlled by setting the R X PHASE2 bit When R X PHASE 2 is zero the start of phase 2 is unaffected by the receive transmit frame sync As shown in Figure 11 8 phase 2 starts as soon as phase 1 is finished When R X PHASE2 1 the first phase starts as soon as the frame sync goes active low if FS R X P 1 high if FS R X P 0 T...

Page 345: ... field in the R X CR supports up to 128 elements per frame as shown in Table 11 10 R X PHASE 0 selects a single phase data frame and R X PHASE 1 selects a dual phase frame for the data stream For a single phase frame the value of FRLEN2 does not matter Program the frame length fields with w minus 1 where w represents the number of elements per frame For Figure 11 8 R X FRLEN1 1 or 0000001b and R X...

Page 346: ...1 11 McBSP Receive Transmit Element Length Configuration R X WDLEN 1 2 McBSP Element Length Bits 000 8 001 12 010 16 011 20 100 24 101 32 110 Reserved 111 Reserved 11 3 4 6 Data Packing using Frame Length and Element Length The frame length and element length can be manipulated to effectively pack data For example consider a situation in which four 8 bit elements are trans ferred in a single phase...

Page 347: ...ata element as shown in Figure 11 11 In this case R X PHASE 0 indicating a single phase frame R X FRLEN1 0b indicating a 1 element frame R X WDLEN1 101b indicating 32 bit elements In this situation one 32 bit data element is transferred to and from the McBSP by the CPU or the DMA controller Thus one read of DRR and one write of DXR is necessary for each frame As a result the number of transfers is...

Page 348: ...ata delay 2 data delay 1 D R X data delay 0 D R X FS R X CLK R X Á Á Á Á Á Á 0 bit period 2 bit period 1 bit period Normally a frame sync pulse is detected or sampled with respect to an edge of serial clock CLK R X Thus on a subsequent cycle depending on data delay value data can be received or transmitted However in the case of a 0 bit data delay the data must be ready for reception and or transm...

Page 349: ...a ap pears after a 2 bit delay The serial port essentially discards the framing bit from the data stream as shown in Figure 11 13 In transmission by delaying the first transfer bit the serial port essentially inserts a blank period a high impedance period in place of the framing bit Here it is expected that the framing device in serts its own framing bit or that the framing bit is generated by ano...

Page 350: ... are used R X DATDLY 01b indicating a data delay of one bit clock Figure 11 14 AC97 Dual Phase Frame Format D R X FS R X P2E12 P2E11 P2E10 P2E9 P2E8 P2E7 P2E6 P2E5 P2E4 P2E3 P2E2 P2E1 P1E1 20 bits 16 bits 1 bit data delay Á Á PxEy denotes phase x and element y Figure 11 14 shows the AC97 timing near frame synchronization First the frame sync pulse itself overlaps the first element In McBSP operati...

Page 351: ... from 1 to 128 R X FRLEN1 00h to 7Fh The required serial element length is set in the R X WDLEN1 field in the R X CR If a dual phase frame is required for the transfer RPHASE 1 and each R X FRLEN 1 2 can be set to any value between 00h and 7Fh Figure 11 16 shows a single phase data frame of one 8 bit element Since the transfer is configured for a 1 bit data delay the data on the DX and DR pins are...

Page 352: ... This indicates that the receive data register DRR is ready with the data to be read by the CPU or the DMA controller RRDY is deactivated when the DRR is read by the CPU or the DMA controller Figure 11 17 Receive Operation ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read of DRR B RBR to DRR copy B Read of DRR A RBR to DRR copy A RRDY DR FSR C5 C6 C7 B0 B2 B3 B4 B5 B6 B7 A0 A1 B1 CLKR 1...

Page 353: ...y decreasing the time between frame synchronization signals in bit clocks which is limited only by the number of bits per frame As the frame transmit frequency is increased the inactivity period between the data frames for adjacent transfers decreases to 0 The minimum time between frame synchronization pulses is the number of bits transferred per frame This time also defines the maximum frame freq...

Page 354: ... of data transmitted is asynchronous to CLKX as shown in Figure 11 12 11 3 6 Frame Synchronization Ignore The McBSP can be configured to ignore transmit and receive frame synchro nization pulses The R X FIG bit in the R X CR can be set to 0 to recognize frame sync pulses or it can be set to 1 to ignore frame sync pulses This way you can use R X FIG either to pack data if operating at maximum frame...

Page 355: ...ored XFIG 0 an unexpected FSX pulse aborts the ongoing transmission sets the XSYNCERR bit in the SPCR to 1 and reiniti ates transmission of the current element that was aborted When XFIG 1 unexpected frame sync signals are ignored Figure 11 20 shows that element B is interrupted by an unexpected frame sync pulse when R X FIG 0 The reception of B is aborted B is lost and a new data element C is rec...

Page 356: ...onization signals are ignored by setting R X FIG 1 Here the transfer of element B is not affected by an unexpected frame synchronization Figure 11 21 Unexpected Frame Synchronization With R X FIG 1 R X SYNCERR low A0 D R X FS R X C4 C5 C6 B0 B1 B2 B3 B4 B5 B6 B7 C7 CLK R X Frame synchronization ignored ...

Page 357: ... element This stream takes one read transfer and one write trans fer for each 8 bit element Figure 11 23 shows the McBSP configured to treat this stream as a continuous stream of 32 bit elements In this example R X FIG is set to 1 to ignore unexpected subsequent frames Only one read transfer and one write transfer is needed every 32 bits This configuration effectively reduces the required bus band...

Page 358: ...tion 11 40 Figure 11 23 Data Packing at Maximum Frame Frequency With R X FIG 1 Frame ignored Frame ignored Frame ignored Frame ignored Frame ignored Frame ignored DXR to XSR copy DX FSX CLKX RBR to DRR copy DR Element 1 FSR CLKR ...

Page 359: ... if an RBR to DRR copy is complete Therefore if DRR has not been read by the CPU or the DMA controller since the last RBR to DRR transfer RRDY 1 an RBR to DRR copy does not take place until RRDY 0 This prevents an RSR to RBR copy New data arriving on the DR pin is shifted into RSR and the pre vious contents of RSR is lost After the receiver starts running from reset a minimum of three elements mus...

Page 360: ...RBR to DRR copy B RBR to DRR copy A No Read of DRR A No RSR to RBR copy C No Read of DRR A CLKR FSR DR RRDY RFULL Figure 11 25 shows the case in which RFULL is set but the overrun condition is averted by reading the contents of DRR at least two and a half cycles before the next element C is completely shifted into RSR This ensures that a RBR to DRR copy of data B occurs before the next element is ...

Page 361: ...erial port is in the inter packet intervals The programmed data delay RDATDLY for reception may start during these inter packet in tervals for the first bit of the next element to be received Thus at maxi mum frame frequency frame synchronization can still be received RDATDLY bit clocks before the first bit of the associated element For this case reception continues normally because these are not ...

Page 362: ...re frame pulse Receiver continues running Start receiving data sync pulse occurs Receive frame Case 1 Case 2 Case 3 Figure 11 27 Unexpected Receive Synchronization Pulse ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RSYNCERR RRDY DR FSR C1 C0 B7 A0 CLKR Unexpected frame synchronization RBR to DRR copy Read of D...

Page 363: ... A1 Write of DXR E DXR to XSR copy D Write of DXR C DXR to XSR copy B XRDY DX FSX B7 A0 CLKX 11 3 7 4 Transmit Empty XEMPTY XEMPTY indicates whether the transmitter has experienced under flow Either of the following conditions causes XEMPTY to become active XEMPTY 0 During transmission DXR has not been loaded since the last DXR to XSR copy and all bits of the data element in the XSR have been shif...

Page 364: ...ed on DX if you fail to reload the DXR before the subsequent frame synchronization Figure 11 30 shows the case of writing to DXR just be fore a transmit underflow condition that would otherwise occur After B is trans mitted C is written to DXR before the next transmit frame sync pulse occurs so that C is successfully transmitted on DX averting a transmit empty condi tion Figure 11 29 Transmit Empt...

Page 365: ...on continues Case 2 FSX pulses with normal serial port transmission This situation is discussed in section 11 3 5 3 There are two possible reasons for a trans mit not to be in progress J This FSX pulse is the first one to occur after XRST 1 J The serial port is in the interpacket intervals The programmed data delay XDATDLY may start during these interpacket intervals before the first bit of the ne...

Page 366: ...is set XSYNCERR can be cleared only by transmitter reset or by writing a 0 to this bit in the SPCR If XINTM 11b in the SPCR XSYNCERR drives the receive interrupt XINT to the CPU Note The XSYNCERR bit in the SPCR is a read write bit so writing a 1 to it sets the error condition Typically writing a 0 is expected Figure 11 32 Unexpected Transmit Frame Synchronization Pulse A1 B2 B3 B4 B5 B6 B7 B4 B5 ...

Page 367: ...ample Data ABCh RJUST value Justification Extension Value in DRR 00 Right Zero fill MSBs 0000 0ABCh 01 Right Sign extend MSBs FFFF FABCh 10 Left Zero fill LSBs ABC0 0000h 11 Reserved Reserved Reserved 11 3 9 32 Bit Bit Reversal R X WDREVRS The 32 bit bit reversal feature is only available for the C6211 C6711 device Normally all transfers are sent and received with the MSB first However if you set ...

Page 368: ...n 8 bit serial data stream If companding is enabled and either phase of the frame does not have an 8 bit element length companding continues as if the element length is eight bits When companding is used transmit data is encoded according to the specified companding law and receive data is decoded to 2s complement format Companding is enabled and the desired format is selected by appropriately set...

Page 369: ...e SPCR as shown in Table 11 13 Table 11 13 Justification of Expanded Data in DRR DRR Bits RJUST 31 16 15 0 00 0 LAW16 01 sign LAW16 10 LAW16 0 11 Reserved 11 4 1 Companding Internal Data If the McBSP is otherwise unused the companding hardware can compand internal data This hardware can be used to Convert linear data to the appropriate µ law or A law format Convert µ law or A law data to the linea...

Page 370: ...d transmit interrupts RINT when RINTM 0 and XINT when XINTM 0 or synchronization events REVT and XEVT allow synchronization of the CPU or the DMA controller to these conversions respectively Here the time for this companding depends on the serial bit rate selected Figure 11 36 Companding of Internal Data ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DLB From CPU DMA con...

Page 371: ... circuitry Figure 11 37 Clock and Frame Generation 0 1 1 0 CLKXM 0 1 Inset FSX pin FSR pin CLKR pin CLKX pin FSG FSX_int CLKX_int Frame selection Clock selection R X IOEN CLKG FSR_int CLKS pin internal clock source DXR to XSR FSGM 0 1 FSR_int CLKR_int FSRP 1 0 0 1 FSRM FSRM GSYNC FSRP 0 1 FSXP See inset FSXP FSXM FSXM generator Sample rate Receive Transmit DLB CLKRM CLKRM CLKXM CLKRP CLKRP CLKXP C...

Page 372: ...k divide down CLKGDV The number of input clocks per data bit clock Frame period FPER The frame period in data bit clocks Frame width FWID The width of an active frame pulse in data bit clocks In addition a frame pulse detection and clock synchronization module allows synchronization of the clock divide down with an incoming frame pulse The operation of the sample rate generator during device reset...

Page 373: ...ng but is resynchronized and the frame sync signal FSG is generated only after the receive frame synchronization sig nal FSR is detected Also the frame period FPER is a don t care because the period is dictated by the external frame sync pulse 11 5 2 4 CLKSP CLKS polarity clock edge select Used only when the external clock CLKS drives the sample rate generator clock CLKSM 0 CLKSP 0 The rising edge...

Page 374: ... 2 internal clock and FSG is driven inactive The internal clock source for the C6211 C6711 is CPU clock while the internal clock source for C6211 C6711 is CPU 2 clock half of the CPU clock frequency CLKG and FSG are inactive when GRST 0 If necessary set R X RST 0 2 Program SRGR as required If necessary other control registers can be written with desired values if the respective portion R X is in r...

Page 375: ...ternal clock input CLKSM 0 CLKS as the source for the sample rate generator input clock Any divide periods are divide downs calculated by the sample rate generator and are timed by this input clock selection The McBSP cannot run faster than half of the CPU clock frequency Therefore when CLKSM 1 the minimum value of CLKGDV should be 1 for the C6201 C6202 C6701 For the C6211 C6711 even if CLKSM 1 yo...

Page 376: ...NC 1 ensures that the McBSP and the external device to which it is communicat ing are dividing down the CLKS with the same phase relationship If GSYNC 0 this feature is disabled and CLKG runs freely and is not resynchronized If GSYNC 1 an inactive to active transition on FSR triggers a resynchronization of CLKG and the generation of FSG CLKG always begins at a high state after synchronization Also...

Page 377: ...When GSYNC 1 and CLKGDV 1 FSR external FSRP 1 FSG CLKG needs resync CLKG no need to resync FSR external FSRP 0 CLKS CLKSP 0 CLKS CLKSP 1 Figure 11 41 CLKG Synchronization and FSG Generation When GSYNC 1 and CLKGDV 3 FSR external FSRP 1 FSG CLKG needs resync CLKG no need to resync FSR external FSRP 0 CLKS CLKSP 0 CLKS CLKSP 1 ...

Page 378: ... DR FSR and CLKR are internally connected through multiplexers to DX FSX and CLKX respectively as shown in Figure 11 37 DLB mode allows testing of se rial port code with a single DSP device 11 5 2 6 Receive Clock Selection DLB CLKRM Table 11 15 shows how the digital loopback bit DLB and the CLKRM bit in the PCR select the receiver clock In digital loopback mode DLB 1 the transmitter clock drives t...

Page 379: ...on is independently programmable for the receiver and the transmitter for all data delay values When set to 1 the FRST bit in the SPCR activates the frame generation logic to generate frame sync signals provided that FSGM 1 in SRGR The frame sync programming options are A frame pulse with a programmable period between sync pulses and a pro grammable active width specified in the sample rate genera...

Page 380: ...e frame pulse width ranging from 1 to 256 data bit clocks At the same time the frame period value FPER 1 is also counting down and when this value reaches 0 FSG goes high again indicating a new frame is beginning Thus the value of FPER 1 determines a frame length from 1 to 4096 data bits When GSYNC 1 the value of FPER does not matter Figure 11 42 shows a frame of 16 CLKG periods FPER 15 or 0000111...

Page 381: ... sync input on FSR is used to synchro nize CLKG and generate FSG 1 0 0 FSX_int drives FSR_int FSX is selected as shown in Table 11 18 High impedance 1 X 1 FSX_int drives FSR_int and is selected as shown in Table 11 18 Input External FSR is not used for frame synchronization but is used to synchronize CLKG and gener ate FSG since GSYNC 1 1 1 0 FSX_int drives FSR_int and is selected as shown in Tabl...

Page 382: ...ection of frame synchronization the receive and transmit CPU interrupts RINT and XINT can be programmed to detect frame synchroniza tion by setting RINTM XINTM 10b in the SPCR Unlike other types of serial port interrupts this one can operate while the associated portion of the serial port is in reset for example RINT can be activated while the receiver is in re set In that case the FS R X M and FS...

Page 383: ...form a minimum pulse width CLKSM 0 external clock CLKS drives the sample rate generator CLKSP 1 falling edge of CLKS generates CLKG and thus CLK R X _int CLKGDV 1 receive clock shown as CLKR is half of CLKS frequency FS R X P 1 active low frame sync pulse R X FRLEN1 11111b 32 elements per frame R X WDLEN1 0 8 bit element R X PHASE 0 single phase frame and thus R X FRLEN2 R X WDLEN2 X R X DATDLY 0 ...

Page 384: ...e E2B7 E1B0 E1B1 E1B2 E1B3 E1B4 E1B5 E1B6 E1B7 E2B7 E1B0 E1B1 E1B2 E1B3 E1B4 E1B5 E1B6 E1B7 E32B0 CLKG CLKR_int CLKX_int first FSR DR DX subsequent FSR CLKG CLKR_int CLKX_int subsequent FSR DR DX first FSR FSG FSR_int FSX_int FSR external CLKS Sample point The rising edge of CLKS detects the external FSR This external frame sync pulse resynchronizes the internal McBSP clocks and generates the fram...

Page 385: ...nd CLKX_int frequencies are half of the CLKS frequency GSYNC 0 CLKS drives CLKG CLKG runs freely and is not resynchro nized by FSR FS R X M 0 Frame synchronization is externally generated The fram ing pulse is wide enough to be detected FS R X P 0 Active high input frame sync signal R X DATDLY 1 Specifies a data delay of one bit Figure 11 45 Double Rate Clock Example E2B7 E1B0 E1B1 E1B2 E1B3 E1B4 ...

Page 386: ...t of the element RBR is not copied to DRR upon reception of the last bit of the element Thus RRDY is not set active This feature also implies that no interrupts or synchro nization events are generated for this element If a transmit element is not enabled DX is in the high impedance state A DXR to XSR transfer is not automatically triggered at the end of serial transmission of the related element ...

Page 387: ... masking DX is always driven during transmission of data DX is masked or driven to hi Z during inter packet intervals when a channel is masked regardless of whether it is enabled or when an element is disabled XMCM 01b All elements are disabled and therefore masked by default Required elements are selected by enabling XP A B BLK and XCER appropri ately and these selected elements are not masked DX...

Page 388: ...element 15 XCBLK 001b Subframe 1 Element 16 to element 31 XCBLK 010b Subframe 2 Element 32 to element 47 XCBLK 011b Subframe 3 Element 48 to element 63 XCBLK 100b Subframe 4 Element 64 to element 79 XCBLK 101b Subframe 5 Element 80 to element 95 XCBLK 110b Subframe 6 Element 96 to element 111 XCBLK 111b Subframe 7 Element 112 to element 127 11 6 3 2 RPBBLK Receive partition B subframe RPBBLK 00b S...

Page 389: ... the available 128 elements can be enabled at any given time The 128 elements comprise eight subframes 0 through 7 and each sub frame has 16 contiguous elements Further even numbered subframes 0 2 4 and 6 belong to partition A and odd numbered subframes 1 3 5 and 7 be long to partition B The number of elements enabled can be updated during the course of a frame to allow any arbitrary group of elem...

Page 390: ...is enabled When an element is disabled Following are descriptions of how each XMCM value affects operation XMCM 00b The serial port transmits data over the DX pin for the number of elements programmed in XFRLEN1 Thus DX is driven during transmit XMCM 01b Only those elements that need to be transmitted are se lected via XP A B BLK and XCER Only these selected elements are writ ten to DXR and ultima...

Page 391: ...number of elements selected in RCER and not the number of elements programmed in RFRLEN1 For transmitting the same subframe that is used for reception is used to maintain symmetry so the value XP A B BLK does not matter DXR is loaded and DXR to XSR copy occurs for all the elements that are enabled via RP A B BLK However DX is driven only for those elements that are selected via XCER The elements e...

Page 392: ...eration a XMCM 00b DXR to XSR E0 Write of DXR E1 DXR to XSR copy E1 Write of DXR E2 DXR to XSR copy E2 DXR to XSR copy E3 E3 E2 E1 Write of DXR E3 XRDY DX E0 FSX b XMCM 01b XPABLK 00b XCER 1010b DXR to XSR E1 Write of DXR E3 DXR to XSR copy E3 E3 E1 XRDY DX FSX ...

Page 393: ... XSR copy E1 Read of DRR E1 RBR to DRR copy E3 E3 DX XRDY d XMCM 11b RPABLK 00b XPABLK X RCER 1010b XCER 1000b RBR to DRR copy E3 Read of DRR E3 RBR to DRR copy E1 E3 E1 RRDY DR FS R X DXR to XSR copy E3 c XMCM 10b XPABLK 00b XCER 1010b DXR to XSR E0 Write of DXR E1 DXR to XSR copy E1 Write of DXR E2 DXR to XSR copy E2 E3 E1 Write of DXR E3 XRDY DX FSX ...

Page 394: ... 14 RCEB 13 RCEB 12 RCEB 11 RCEB 10 RCEB 9 RCEB 8 RCEB 7 RCEB 6 RCEB 5 RCEB 4 RCEB 3 RCEB 2 RCEB 1 RCEB 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCEA 15 RCEA 14 RCEA 13 RCEA 12 RCEA 11 RCEA 10 RCEA 9 RCEA 8 RCEA 7 RCEA 6 RCEA 5 RCEA 4 RCEA 3 RCEA 2 RCEA 1 RCEA 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW ...

Page 395: ...numbered subframe in partition B 11 6 3 2 Changing Element Selection Using the multichannel selection feature a static group of 32 elements can be enabled and remains enabled with no CPU intervention until this allocation is modified An arbitrary number of group of or all of the elements within a frame can be accessed by updating the block allocation registers during the course of the frame in res...

Page 396: ...xtra delay for the DX pin turn on time This feature is useful for McBSP multichannel operations such as in a time division multiplexed TDM system The McBSP supports up to 128 channels in a multichannel operation These channels can be driven by different devices in a TDM data communication line such as the T1 E1 line In any multichannel operation where multiple devices transmit over the same DX lin...

Page 397: ...rs because the dead time between the two devices is not enough You need to apply alternative software or hardware methods to ensure proper multichannel operation in this case If you set DXENA 1 in the second McBSP the second McBSP turns on its DX pin after two CPU clock cycles of extra delay time This ensures that the previous McBSP on the same DX line is disabled before the second McBSP starts dr...

Page 398: ... determined by the presence or absence of the master clock Data transfer is initiated by the detection of the master clock and is terminated on absence of the master clock The slave has to be enabled during this period of transfer When the McBSP is the master the slave enable is derived from the master transmit frame sync pulse FSX Example block diagrams of the McBSP as a master and as a slave are...

Page 399: ...1 55 show the timing diagrams of the two SPI transfer formats and the four timing variations Table 11 21 SPI Mode Clock Stop Scheme CLKSTP CLKXP Clock Scheme 0X X Clock stop mode disabled Clock enabled for non SPI mode 10 0 Low inactive state without delay The McBSP transmits data on the rising edge of CLKX and receives data on the falling edge of CLKR 11 0 Low inactive state with delay The McBSP ...

Page 400: ...Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ If the McBSP is the SPI master CLKXM 1 MOSI DX If the McBSP is the SPI slave CLKXM 0 MOSI DR If the McBSP is the SPI master CLKXM 1 MISO DR If the McBSP is the SPI slave CLKXM 0 MISO DX The CLKSTP and CLKXP fields of the serial port control register SPCR select the appropriate clock scheme for a particular SPI interface as shown in Table 11 21 Th...

Page 401: ...l clock marks the beginning of trans fer in this SPI transfer format The McBSP clock stop mode requires single phase frames R X PHASE 0 and one element per frame R X FRLEN 0 When the McBSP is configured to operate in SPI mode both the transmitter and the receiver operate together as a master or a slave The McBSP is a master when it generates clocks When the McBSP is the SPI master CLKX drives both...

Page 402: ...fore XDATDLY must be programmed to 1 When the McBSP is the SPI master an XDATDLY value of 0 or 2 causes undefined operation As the SPI master the McBSP generates CLKX and FSX through the internal sample rate generator As discussed in section 11 5 2 1 the CLKSM bit in the SRGR should be set to specify either the CPU clock or the external clock input CLKS as the clock source to the internal sample r...

Page 403: ...hat the first data to be transmitted is available on the DX pin The MISO waveform in Figure 11 54 and Figure 11 55 shows how the McBSP transmits data as an SPI slave Setting RDATDLY 0 ensures that the McBSP is ready to receive data from the SPI master as soon as it detects the serial clock CLKX Depend ing on the clock stop mode used data is received at various clock edges ac cording to Table 11 21...

Page 404: ... two bit clocks for the McBSP to reinitialize 5 Write the desired value into the CLKSTP field in the SPCR Table 11 21 shows the various CLKSTP modes 6 Depending on whether the CPU or DMA services the McBSP either a or b should be followed a This step should be performed if the CPU is used to service the McBSP Set XRST RRST 1 to enable the serial port Note that the value written to the SPCR at this...

Page 405: ...only bit that reflects the status of that signal CLK R X M and CLK R X P work similarly for CLK R X When the transmitter is selected as general purpose I O the value of the DX_STAT bit in the PCR is driven onto DX DR is always an input and its value is held in the DR_STAT bit in the PCR To configure CLKS as a general purpose input both the transmitter and receiver have to be in the reset state and...

Page 406: ... 12 2 Timer Registers 12 4 12 3 Resetting the Timer and Enabling Counting GO and HLD 12 7 12 4 Timer Counting 12 8 12 5 Timer Clock Source Selection CLKSRC 12 8 12 6 Timer Pulse Generation 12 9 12 7 Boundary Conditions in the Control Registers 12 11 12 8 Timer Interrupts 12 11 12 9 Emulation Operation 12 11 Chapter 12 ...

Page 407: ...and an output pin The input and output pins TINP and TOUT can function as timer clock input and clock out put They can also be configured for general purpose input and output respectively With an internal clock for example the timer can signal an external A D converter to start a conversion or it can trigger the DMA controller to begin a data transfer With an external clock the timer can count ext...

Page 408: ... output TINT timer interrupt to CPU and DMA ÁÁ ÁÁ ÁÁ ÁÁ CLKSRC HLD 0 1 Peripheral Bus to CPU and DMA ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Equals comparator Count zero GO ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Edge detect Count enable ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Timer period register Timer counter register C P PWID DATOUT HLD Pulse generator ...

Page 409: ...e 12 2 shows the timer control register Table 12 2 describes the fields in this register Figure 12 2 Timer Control Register 31 12 11 10 9 8 Rsvd TSTAT INVINP CLKSRC C P R 0 R 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 HLD GO Rsvd PWID DATIN DATOUT INVOUT FUNC RW 0 RW 0 R 0 RW 0 RW 0 RW 0 RW 0 RW 0 Table 12 2 Timer Control Register Field Descriptions Bitfield Description Section FUNC Function of TOUT pin FUN...

Page 410: ...iod wide 12 6 PWID Pulse width Only used in pulse mode C P 0 PWID 0 TSTAT goes inactive one timer input clock cycle after the timer counter value equals the timer period value PWID 1 TSTAT goes inactive two timer input clock cycles after the timer counter val ue equals the timer period value 12 6 CLKSRC Timer input clock source CLKSRC 0 External clock source drives the TINP pin CLKSRC 1 CPU clock ...

Page 411: ...mber controls the frequency of TSTAT Figure 12 3 Timer Period Register 31 0 Timer Period RW 0 12 2 3 Timer Counter Register The timer counter register Figure 12 4 increments when it is enabled to count It resets to 0 on the next CPU clock after the value in the timer period register is reached Figure 12 4 Timer Counter Register 31 0 Timer Counter RW 0 ...

Page 412: ... before hold The timer counter is not reset Reserved 1 0 Undefined Starting the timer 1 1 Timer counter resets to 0 and starts counting whenever enabled Once set GO self clears Configuring a timer requires three basic steps 1 If the timer is not currently in the hold state place the timer in hold HLD 0 Note that after device reset the timer is already in the hold state 2 Write the desired value to...

Page 413: ... case where the period is 2 and the CPU clock 4 is selected as the timer clock source CLKSRC 1 Once started the timer counts the following sequence 0 0 0 0 1 1 1 1 2 0 0 0 1 1 1 1 2 0 0 0 Note that although the counter counts from 0 to 2 the period is 8 2 4 CPU clock cycles rather than 12 3 4 CPU clock cycles Thus the countdown period is the value of TIMER PERIOD not TIMER PERIOD 1 12 5 Timer Cloc...

Page 414: ... pin when TOUT is used as a timer pin FUNC 1 and may be inverted by setting INVOUT 1 The value actually driven out to the TOUT pin is reflected by DAT OUT Table 12 4 gives equations for various TSTAT timing parameters in pulse and clock modes Figure 12 5 Timer Operation in Pulse Mode C P 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 2 timer clock source period PWID 1 Timer counter ...

Page 415: ...idth Low Pulse f clock source timer period register PWID 1 timer period register PWID 1 Pulse timer period register f clock source f clock source f clock source f clock source 2 timer period register timer period register timer period register Clock 2 timer period register f clock source f clock source f clock source ...

Page 416: ...isters of an active timer Writes from the peripheral bus over ride register updates to the counter register and new status updates to the control register 4 Small timer period values in pulse mode Note that small periods in pulse mode can cause TSTAT to remain high This condition occurs when TIMER PERIOD PWID 1 12 8 Timer Interrupts The TSTAT signal directly drives the CPU interrupt as well as a D...

Page 417: ... chapter describes the interrupt selector and registers available Topic Page 13 1 Available Interrupt Sources 13 2 13 2 External Interrupt Signal Timing 13 5 13 3 Interrupt Selector Registers 13 7 13 4 Configuring the Interrupt Selector 13 10 Chapter 13 ...

Page 418: ...r system needs to use The interrupt selec tor also allows you to effectively change the polarity of external interrupt inputs Table 13 1 lists the available interrupts Note that this table is similar to the DMA synchronization events in Chapter 4 DMA Controller except for two dif ferences One difference is that the McBSP generates separate interrupts and DMA synchronization events The second diffe...

Page 419: ...ernal interrupt pin 6 00111b EXT_INT7 External interrupt pin 7 01000b DMA_INT0 DMA channel 0 interrupt 01001b DMA_INT1 DMA channel 1 interrupt 01010b DMA_INT2 DMA channel 2 interrupt 01011b DMA_INT3 DMA channel 3 interrupt 01100b XINT0 McBSP 0 transmit interrupt 01101b RINT0 McBSP 0 receive interrupt 01110b XINT1 McBSP 1 transmit interrupt 01111b RINT1 McBSP 1 receive interrupt 10000b Reserved 100...

Page 420: ... Interrupt Generation Table 13 2 TMS320C6211 C6711 Available Interrupts Interrupt Selection Number Interrupt Acronym Interrupt Description 00000b DSPINT Host port host to DSP interrupt 00001b TINT0 Timer 0 interrupt 00010b TINT1 Timer 1 interrupt 00011b SD_INT EMIF SDRAM timer interrupt 00100b EXT_INT4 External interrupt 4 00101b EXT_INT5 External interrupt 5 00110b EXT_INT6 External interrupt 6 0...

Page 421: ...elated interrupt flag IF4 is set The earliest cycle that the interrupt can be scheduled is one CLKOUT1 cycle after IF4 is set This is indicated by the active internal interrupt acknowledge IACK signal as shown in Figure 13 1 The interrupt can be postponed or in hibited if not properly enabled as described in other chapters of the CPU Refer ence Guide In that case IACK will be also be postponed Alo...

Page 422: ... 13 1 Timing of External Interrupt Related Signals 0100 INUM_int IACK pin INUM pins IF4 IACK_int EXT_INT4 pin 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 INT4_int CLKOUT2 CLKOUT1 2 3 CLKOUT1 3 CLKOUT1 0100 CLKOUT 2 2X CLKOUT 2 4X CLKOUT 2 ...

Page 423: ...ernal Interrupt Polarity Register The external interrupt polarity register allows you to change the polarity of the four external interrupts EXT_INT4 to EXT_INT7 When XIP is its default value of 0 a low to high transition on an interrupt source is recognized as an interrupt By setting the related XIP bit in this register to 1 you can invert the external inter rupt source and effectively have the C...

Page 424: ...r Table 13 2 you may map any interrupt source to any CPU interrupt Table 13 4 shows the default mapping of interrupt sources to CPU interrupts Figure 13 3 Interrupt Multiplexer Low Register Diagram 31 30 26 25 21 20 16 Reserved INTSEL9 INTSEL8 INTSEL7 R 0 RW 01001 RW 01000 RW 00111 15 14 10 9 5 4 0 Reserved INTSEL6 INTSEL5 INTSEL4 R 0 RW 00110 RW 00101 RW 00100 Figure 13 4 Interrupt Multiplexer Hi...

Page 425: ...External interrupt pin 6 INT7 INTSEL7 00111b EXT_INT7 External interrupt pin 7 INT8 INTSEL8 01000b DMA_INT0 EDMA_INT DMA Channel 0 Interrupt EDMA interrupt INT9 INTSEL9 01001b DMA_INT1 DMA Channel 1 interrupt INT10 INTSEL10 00011b SD_INT EMIF SDRAM timer interrupt INT11 INTSEL11 01010b DMA_INT2 DMA Channel 2 interrupt INT12 INTSEL12 01011b DMA_INT3 DMA Channel 3 interrupt INT13 INTSEL13 00000b DSP...

Page 426: ...ag register should be cleared by the user after some delay to remove any spurious transitions caused by the configuration You may reconfigure the interrupt selector during other times but spurious inter rupt conditions may be detected by the CPU on the interrupts affected by the modified fields For example if EXT_INT4 is low EXT_INT5 is high and INT9 is remapped from EXT_INT4 to EXT_INT5 the low t...

Page 427: ...1 Power Down Logic This chapter describes the power down modes Topic Page 14 1 Overview 14 2 14 2 Triggering Wake Up and Effects 14 4 14 3 Additional Power Saving Modes for the TMS320C6202 14 6 Chapter 14 ...

Page 428: ...where the entire on chip clock structure including multiple buffers is halted at the output of the PLL see Figure 14 1 PD3 is like PD2 but also disconnects the external clock source CLKIN from reaching the PLL Wake up from PD3 takes longer then wake up from PD2 be cause the PLL needs to be re locked just as it does following power up On the C6201 C6202 C6701 both the PD2 and PD3 signals also asser...

Page 429: ...PD PD3 Internal peripheral Figure 14 2 PWRD Field of the CSR Register 31 16 15 14 13 12 11 10 9 0 rsvd Enabled or non enabled interrupt wake Enabled interrupt wake Pd3 Pd2 Pd1 Table 14 1 Power Down Mode and Wake Up Selection PRWD Power down mode Wake up method 000000 no power down 001001 PD1 wake by an enabled interrupt 010001 PD1 wake by an enabled or non enabled interrupt 011010 PD2 011100 PD3 o...

Page 430: ... an enabled interrupt or any interrupt enabled or not as directed by bits 13 and 14 of the CSR When writing to CSR all bits of the PWRD field should be set at the same time Logic 0 should be used when writing to reserved fields bit 15 of CSR The wake up from PD1 can be triggered by either an enabled interrupt or any interrupt enabled or not The first case is selected by writing a logic 1 to bit 13...

Page 431: ...ock from PLL is halted stopping the internal clock structure from switching and resulting in the entire chip being halted Signal terminal PD is driven high All register and internal RAM contents are preserved All signal terminals behave the same way as during Reset PD3 write logic 11100b to bits 15 10 of the CSR Reset only Input clock to the PLL stops generating clocks Signal terminal PD is driven...

Page 432: ... in power consumption In a device which is as highly integrated as the C6000 series of DSPs a significant amount of power can be consumed in a reset or no activity state just due to the internal clock distribution By selectively turning off unused portions of the device the effects can be minimized Table 14 3 shows the peripheral power down register address location and Figure 14 3 shows the regis...

Page 433: ...ock allowed to clock PDEMIF 1 Internal EMIF clock disabled EMIF is not functional The HOLD condition which exists at power down will remain active and external clocks continue to clock 14 3 PDMCSP0 Enable disable internal McBSP0 clock PDMCSP0 0 Internal McBSP0 clock allowed to clock PDMCSP0 1 Internal McBSP0 clock disabled McBSP0 is not functional 14 3 PDMCSP1 Enable disable internal McBSP1 clock ...

Page 434: ...oes not need the serial ports the ports can be disabled and then re enabled when needed When re enabling any of the PD bits the CPU should wait at least 5 additional clock cycles before attempting to access that peripheral This delay can be ac complished with a NOP 5 after any write to a peripheral power down register as shown in Example 14 1 Example 14 1 Assemble Code for Initializing Peripheral ...

Page 435: ...ower inputs The term JTAG as used in this book refers to TI scan based emulation which is based on the IEEE 1149 1 standard Topic Page 15 1 Designing Your Target System s Emulator Connector 14 Pin Header 15 2 15 2 Bus Protocol 15 3 15 3 IEEE 1149 1 Standard 15 3 15 4 JTAG Emulator Cable Pod Logic 15 4 15 5 JTAG Emulator Cable Pod Signal Timing 15 5 15 6 Emulation Timing Calculations 15 6 15 7 Conn...

Page 436: ...cable lead for pin 6 is present in the cable and is grounded as shown in the sche matics and wiring diagrams in this document Table 15 1 14 Pin Header Signal Descriptions Signal Description Emulator State Target State TMS Test mode select O I TDI Test data input O I TDO Test data output I O TCK Test clock TCK is a 10 368 MHz clock source from the emulation cable pod This signal can be used to driv...

Page 437: ...tely a half TCK cycle setup to the next device s TDI signal This type of timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge The penalty for this timing scheme is a reduced TCK frequency The IEEE 1149 1 specification does not provide rules for bus master emula tor devices Instead it states that it expects a bus master to provide bus slave ...

Page 438: ...d TDI can be generated from the falling edge of TCK_RET according to the IEEE 1149 1 bus slave device timing rules Signals TMS and TDI are series terminated to reduce signal reflections A 10 368 MHz test clock source is provided You may also provide your own test clock for greater flexibility Figure 15 2 JTAG Emulator Cable Pod Interface 100 Ω TL7705A RESIN 270 Ω JP2 180 Ω TCK_RET Pin 9 EMU1 Pin 1...

Page 439: ...arantee these timings The emulator pod uses TCK_RET as its clock source for internal synchroni zation TCK is provided as an optional target system test clock source Figure 15 3 JTAG Emulator Cable Pod Timings TDO TMS TDI TCK_RET 6 5 4 3 2 1 1 5 V Table 15 2 Emulator Cable Pod Timing Parameters No Reference Description Min Max Units 1 tc TCK TCK_RET period 35 200 ns 2 tw TCKH TCK_RET high pulse dur...

Page 440: ...0 Given in Table 15 2 on page 15 5 td TMSmax Emulator TMS TDI delay from TCK_RET low maximum 20 ns tsu TDOmin TDO setup time to emulator TCK_RET high minimum 3 ns There are two key timing paths to consider in the emulation design The TCK_RET to TMS TDI path called tpd TCK_RET TMS TDI and The TCK_RET to TDO path called tpd TCK_RET TDO Of the following two cases the worst case path delay is calculat...

Page 441: ...s 10ns 1 35nsƫ 0 4 78 4ns 12 7 MHz tpd TCK_RET TDO ƪtd TTDO tsu TDOmin td bufmax ƫ t ǒTCKfactorǓ 70ns 14 3 MHz 15ns 3ns 10ns 0 4 In this case the TCK_RET to TMS TDI path is the limiting factor In a multiprocessor application it is necessary to ensure that the EMU0 1 lines can go from a logic low level to a logic high level in less than 10 µs This can be calculated as follows tr 5 Rpullup Ndevices ...

Page 442: ...and EMU1 signals are applied only as inputs to the XDS510 emulator header 15 7 1 Buffering Signals If the distance between the emulation header and the JTAG target device is greater than six inches the emulation signals must be buffered If the distance is less than six inches no buffering is necessary The following illustrations depict these two situations No signal buffering In this situation the...

Page 443: ...gnal rise time of less than 10 µs A 4 7 kΩ resistor is suggested for most applications J The input buffers for TMS and TDI should have pullup resistors con nected to VCC to hold these signals at a known value when the emula tor is not connected A resistor value of 4 7 kΩ or greater is suggested J To have high quality signals especially the processor TCK and the emulator TCK_RET signals you may hav...

Page 444: ...Device TCK TDO TDI TMS TRST EMU1 EMU0 Greater Than 6 Inches VCC Note When the TMS TDI lines are buffered pullup resistors should be used to hold the buffer inputs at a known level when the emulator cable is not connected There are two benefits to having the target system generate the test clock The emulator provides only a single 10 368 MHz test clock If you allow the target system to generate you...

Page 445: ... TCK signals should be buffered through the same physical package for better control of timing skew The input buffers for TMS TDI and TCK should have pullup resistors con nected to VCC to hold these signals at a known value when the emulator is not connected A resistor value of 4 7 kΩ or greater is suggested Buffering EMU0 and EMU1 is optional but highly recommended to provide isolation These are ...

Page 446: ...pproximately 3 feet 10 inches Figure 15 6 and Figure 15 7 page 15 13 show the mechanical dimensions for the target cable pod and short cable Note that the pin to pin spacing on the connector is 0 100 inches in both the X and Y planes The cable pod box is nonconductive plastic with four recessed metal screws Figure 15 6 Pod Connector Dimensions 0 90 2 70 4 50 9 50 Refer to Figure 15 7 Emulator Cabl...

Page 447: ... JTAG Emulation Figure 15 7 14 Pin Connector Dimensions 0 100 Key Pin 6 0 100 0 87 0 66 0 20 Pins 2 4 6 8 10 12 14 Pins 1 3 5 7 9 11 13 Cable Connector Side View Connector Front View Cable Note All dimensions are in inches and are nominal dimensions unless otherwise specified ...

Page 448: ...olerance and isolation than a single scan path Since an SPL has the capability of adding all secondary scan paths to the main scan path simultaneously it can support global emulation operations such as starting or stopping a selected group of processors TI emulators do not support the nesting of SPLs for example an SPL connected to the secondary scan path of another SPL However you can have multip...

Page 449: ...SPL s DTCK signal The TMS signal on each device on the secondary scan path is driven by the respec tive DTMS signals on the SPL DTDO on the SPL is connected to the TDI signal of the first device on the sec ondary scan path DTDI on the SPL is connected to the TDO signal of the last device in the secondary scan path Within each secondary scan path the TDI signal of a device is connected to the TDO s...

Page 450: ...m 10 ns td bufmin Target buffer delay minimum 1 ns t bufskew Target buffer skew between two devices in the same package td bufmax td bufmin 0 15 1 35 ns t TCKfactor Assume a 40 60 duty cycle clock 0 4 40 Given in the SPL data sheet td DTMSmax SPL DTMS DTDO delay from TCK low maximum 31 ns tsu DTDLmin DTDI setup time to SPL TCK high minimum 7 ns td DTCKHmin SPL DTCK delay from TCK high minimum 2 ns...

Page 451: ... 3 MHz tpd ǒTCK DTDIǓ ƪtd ǒTTDOǓ td ǒDTCKLmaxǓ tsu ǒDTDLminǓƫ tǒTCKfactorǓ 15ns 16ns 7ns 0 4 9 5ns 10 5 MHz In this case the TCK to DTMS DTDL path is the limiting factor Case 2 Single multiprocessor DTMS DTDO TCK buffered input DTDI buffered out put DTMS DTDO timed from TCK low tpd TCK TDMS ƪtd DTMSmax tǒDTCKHminǓ tsu TTMS t bufskew ƫ tǒTCKfactorǓ 31ns 2ns 10ns 1 35ns 0 4 110 9ns 9 0 MHz tpd TCK D...

Page 452: ...totem pole operation then these devices can be damaged The emulation software detects and prevents this condition However the emulation software has no control over external sources on the EMU0 1 signal Therefore all external sources must be inactive when any device is in the external count mode TI devices can be configured by software to halt processing if their EMU0 1 pins are driven low This fe...

Page 453: ...this figure is suggested Rising edges slower than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used These seven important points apply to the circuitry shown in Figure 15 9 and Figure 15 10 and the timing shown in Figure 15 11 Open collector drivers isolate each board The EMU0 1 pins are tied to ...

Page 454: ...he internal counter EMU0 becomes a processor halted signal During a RUNB or other external analysis count the EMU0 1 IN signal to all boards must remain in the high disabled state You must provide some type of external input XCNT_ENABLE to the PAL to disable the PAL from driving EMU0 1 IN to a low state If sources other than TI processors such as logic analyzers are used to drive EMU0 1 their sign...

Page 455: ...modification EMU0 1 OUT Device Device EMU0 1 1 n Device Device 1 n Up to m boards Notes 1 The low time on EMUx IN should be at least one TCK cycle and less than 10 ms Software will set the EMUx OUT pin to a high state 2 To enable the open collector driver and pullup resistor on EMU1 to provide rising falling edges of less than 25 ns the modification shown in this figure is suggested Rising edges s...

Page 456: ...llup Resistor EMU0 1 Device Device EMU0 1 1 n Device Device 1 n Target Board m Target Board 1 Pullup Resistor Pullup Resistor Note The open collector driver and pullup resistor on EMU1 must be able to provide rising falling edges of less than 25 ns Rising edges slower than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debu...

Page 457: ...15 13 TBC Emulation Connections for n JTAG Scan Paths JTAG0 JTAGN TDI EMU1 TMS TDO EMU0 TRST TCK TDO TCK TRST EMU1 EMU0 TMS TDI Clock TDI1 TDI0 TCKO TMS5 EVNT3 TMS4 EVNT2 TMS3 EVNT1 TMS2 EVNT0 TMS1 TMS0 TDO TCKI VCC TBC In the system design shown in Figure 1 13 the TBC emulation signals TCKI TDO TMS0 TMS2 EVNT0 TMS3 EVNT1 TMS5 EVNT3 TCKO and TDI0 are used and TMS1 TMS4 EVNT2 and TDI1 are not conne...

Page 458: ...ce on the main JTAG scan path TDI0 on the TBC is connected to the TDO signal of the last device on the main JTAG scan path Within the main JTAG scan path the TDI signal of a device is connected to the TDO signal of the device before it TRST for the devices can be generated either by inverting the TBC s TMS5 EVNT3 signal for software control or by logic on the board itself ...

Page 459: ...25 programmable 5 3 sorting 5 26 transferring a large single block 5 25 address generation hardware 6 17 address mapping internal data RAM 3 7 RAM in cache mode 3 5 address modification 6 14 address phase Ta 8 36 Address pin EA 12 9 6 address range 6 9 address shift 9 32 address signals 8 3 8 10 address space 1 6 address update mode 6 22 addresses must be aligned 6 27 adjustment address 5 22 align...

Page 460: ... boot mode pins 10 3 boot process 10 8 HPI boot process 10 9 memory at reset address 10 8 memory map 10 5 overview 10 2 ROM boot process 10 8 TMS320C6211 summary 10 5 boot configuration control via expansion bus 8 49 bootload note on program memory 2 6 TMS320C6202 3 6 bootload operation 3 6 BSP serial port control extension register SPCE CLKP bit 11 13 FSP bit 11 12 buffered signals JTAG 15 9 buff...

Page 461: ...interrupt selector 13 10 connector 14 pin header 15 2 dimensions mechanical 15 12 DuPont 15 3 contention on the data bus 8 10 contiguous elements 6 5 control and status register CSR 2 3 4 6 4 9 control pins SDRAM 9 23 control register boundary conditions 12 11 control registers 1 9 4 2 8 4 9 5 9 6 9 9 EDMA 6 6 control status register 3 4 figure iii controller 2 3 data memory 1 6 direct memory acce...

Page 462: ...1 determining ready status 11 21 device reset 10 2 11 19 diagnostic applications 15 23 diagram expansion bus block 8 2 expansion bus host port interface block 8 22 expansion bus interface in the TMS320C6202 8 4 expansion bus XCE 0 1 2 3 space control register 8 9 host port interface block of TMS320C6211 7 5 internal memory block 4 3 L1D 2 way set associative cache diagram 4 11 L1P direct mapped ca...

Page 463: ... channel transfer 6 34 EDMA channels 6 34 EDMA control registers table 6 6 EDMA Controller figure 6 3 EDMA controller 1 10 6 6 6 8 6 25 6 28 6 32 6 34 7 3 TMS320C6211 13 4 EDMA DST Address Parameter Updates table 6 31 EDMA Element and Frame Line Count Updates table 6 28 EDMA interrupt generation 6 32 EDMA interrupt servicing by the CPU 6 34 EDMA parameter RAM 6 16 6 18 6 28 EDMA Parameter RAM Cont...

Page 464: ...ster ER figure 6 7 event register ER 6 6 Event Set Register ESR figure 6 8 event set register ESR 6 6 6 7 event set register ESR 6 17 event triggered EDMA 6 17 events synchronization 11 7 example dual phase frame 11 26 Example of the Expansion Bus Interface to Four 8 Bit FIFOs figure 8 11 Example of the Expansion Bus Interface to Two 16 Bit FIFOs figure 8 12 examples DMA single frame transfer 8 20...

Page 465: ...External Device Requests the Bus From C6202 Using XBOFF Note that internal bus arbiter is enabled figure 8 33 external interfaces 9 6 external interrupt signal timing 13 5 external IO port accesses 8 10 external memory 3 6 10 2 external memory interface 3 7 external memory interface EMIF 1 8 1 9 2 3 3 3 3 7 4 2 8 3 8 4 9 5 9 6 16 bit ROM 9 53 ASRAM parameters 9 53 asynchronous writes 9 56 asynchro...

Page 466: ...5 SPCR 11 8 fields L2 flush register 4 22 FIFO control register 8 6 FIFO Read Mode Read Timing glue less case figure 8 17 FIFO Read Mode With Glue figure 8 18 FIFO Write Cycles figure 8 16 first level memory 4 1 flag monitoring 8 19 flags event 5 18 flow chart L2 cache data request 4 17 flush and clean a range of addresses 4 22 flush base address register 4 5 flush base address register fields 4 8...

Page 467: ...rement 7 20 interrupt to host 7 12 read write select 7 10 ready pin 7 10 registers 7 16 signal descriptions 7 7 software handshaking 7 17 strobes 7 10 write with autoincrement 7 25 write without autoincrement 7 23 HPI 1 10 HPI Block Diagram of TMS320C6211 figure 7 5 HPI bootload 3 6 HPI control register HPIC 7 5 I I O port 8 2 I O port operation 8 10 Idle modes 10 1 13 2 idle modes 14 1 IEEE 1149 ...

Page 468: ...7 signal timing 13 5 source between DSPINT and XFRCT counter 8 25 sources 13 2 TCC to DMA mapping 6 33 timer 0 6 18 xBHC register field DSPINT 8 25 interrupt EDMA transfer complete code 6 18 timer 1 6 18 interrupt enable register 6 32 interrupt multiplexer high register diagram figure 13 8 interrupt multiplexer low register diagram figure 13 8 interrupt pending register 6 32 interrupt processing 6...

Page 469: ... cache L1P 1 7 line frame count FC 6 12 line frame index FIX 6 12 link address 6 16 LINK bit in the options field 6 25 Link Conditions table 6 26 Linked EDMA Transfer figure 6 25 linking EDMA transfers 6 25 linking events 6 13 little endian LE 7 8 lock up or error condition 6 7 logical address bit 0 9 14 logical addressing 8 10 LSB address bits 7 8 M manual start operation 5 13 map of cache addres...

Page 470: ... examples 11 65 companding data formats 11 51 companding DLB method 11 52 companding hardware 11 50 companding nonDLB method 11 52 configuration 11 7 control register 11 7 CPU interrupts 11 22 data delay 11 30 data packing 11 39 data reception 11 18 data transmission 11 18 double rate clock 11 67 double rate ST BUS clock 11 65 element length 11 28 end of block interrupt 11 78 end of frame interrup...

Page 471: ...utput strobes 8 3 overview TMS320 family 1 2 P Packing and unpacking 9 14 page boundaries monitoring 9 25 PAL 15 19 15 20 15 22 parameter entry of an EDMA event 6 12 Parameter RAM 6 10 6 11 parameter RAM 6 24 6 36 parameter RAM PaRAM 6 9 parameter reload space in EDMA parameter RAM 6 21 Parameter Storage for an EDMA Event figure 6 12 parameters of the expansion bus 8 8 pause operation 5 13 PCC fie...

Page 472: ...12 Read Write FIFO Interface With Glue figure 8 16 read write synchronization 6 19 Read Write Synchronized 2 D Transfer No Frame Sync figure 6 23 ready signals 8 27 ready status 11 21 receive buffer register RBR 11 4 receive control register 11 14 receive data clocking figure 11 25 receive data justification 11 49 receive event 6 18 receive interrupt RINT 11 22 receive operation 11 34 receive shif...

Page 473: ...page information 9 27 pin control register PCR 11 6 11 11 receive buffer register RBR 11 4 receive channel enable register RCER 11 6 receive control register RCR 11 14 receive shift register RSR 11 4 reload 5 25 sample rate generator register SRGR 11 6 serial port control register SPCR 11 6 11 7 space control 8 9 timer 12 4 timer counter 12 6 timer period 12 6 transfer counter 5 16 transmit channe...

Page 474: ...buffered 15 9 buffering for emulator connections 15 8 to 15 11 burst last 8 27 bus back off 8 27 byte enable 8 27 8 41 chip select 8 26 8 41 clock input 8 26 control 8 27 8 41 data 8 14 data bus 8 41 description 14 pin header 15 2 EMIF signal descriptions 9 7 expansion bus 8 5 FIFO clock output 8 14 FIFO output enable 8 14 FIFO read enable 8 14 FIFO read enable write enable chip select 8 14 FIFO w...

Page 475: ... serial port control register TSPC TXM bit 11 17 11 55 XRDY bit 11 9 TDM serial port interface 11 78 TDO output 15 3 TDO signal 15 3 15 4 15 6 15 7 15 17 15 23 test bus controller 15 20 15 23 test clock 15 10 The Bus Master Reads a Burst of Data From the C6202 figure 8 39 The Expansion Bus Interface in the TMS320C6202 Block Diagram figure 8 4 The Expansion Bus Master Writes a Burst of Data to the ...

Page 476: ... two level internal memory 4 1 TMS320C6211 Block Diagram 6 2 figure 7 3 TMS320C6211 Boot Configuration Summary table 10 5 TMS320C6211 EMIF CE Space Control Register figure 9 12 TMS320C6211 Internal Memory Block Diagram figure 4 3 TMS320C6211 Internal Memory Configurations table 4 2 TMS320C6211 Memory Map Summary table 10 7 TMS320C6701 cache architecture 3 2 internal memory configuration 3 2 transf...

Page 477: ...itecture 1 1 very long instruction word VLIW 1 1 W wait data phase Tw Td 8 36 wake up from a power down 14 4 word aligned 8 10 word count register 4 8 word index 4 9 write hold 9 12 write hold and read hold bit fields 9 13 write hold fields 9 14 write interface 8 15 write miss 4 9 write strobe 9 12 write transfer 5 2 X XARB bit value 8 44 XBD register 8 7 XBEA register 8 6 8 7 XBHC register 8 6 8 ...

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