PRISM MPI2-25 and MPX2-25 Media Analysis Platform User Manual
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BMCA operation
The Best Master Clock Algorithm (BMCA) is used to choose the active master
on the domain. This is partially explained in the introduction to this document.
The BMCA operation varies somewhat as function of communication mode.
Multicast mode
In Multicast mode, the active master sends announce messages which all other
masters and slaves can receive. So all devices can evaluate the BMCA and
decide on the best master. If any device detects that its BMCA rating is better
than the current master, it will send an announce and take over as the active
master.
Unicast mode
In Unicast mode, slaves only get Announce messages if they establish a grant
from the master. Therefore, each slave must set up a grant with every device in
its AMT. Since the masters do not set up grants from other masters, they do not
have the information to evaluate the BMCA and know if they are the active
master. It is up to the slaves to evaluate the BMCA based on the announce
message they get from each master in their AMT. Each slave then decides
which master is the best and then set up grants for the other message types. If
slaves on a given network have a different list of masters in their AMT, then
they may choose a different master.
Mixed mode
In a SMPTE ST2059 mixed environment, the announce message is Multicast.
Therefore, the BMCA can follow the Multicast conventions.
Compensating for causes of asymmetric delay
Several factors can cause the PTP message delay to be different for the
messages sent from the master to slave as opposed to the messages the other
direction from the slave to master. Unless corrected, this propagation delay
asymmetry will cause an offset in the clock phase equal to ½ the difference in
the two path delays. There are 4 main causes of asymmetric delay: Rate
mismatch in the ports on a switch, Traffic mismatch on the two paths, message
type mismatch, and cable delay variation. This section contains suggestions on
how to design the system to minimize the delay asymmetry. Alternatively,
some slaves provide a way to manually enter a correction value to cancel the
delay error.
Rate mismatch
Rate mismatch in a switch causes a delay asymmetry because the switch
performs a “store and forward” action on messages. This means the entire
message must be stored in the buffer before it starts to be “forwarded” or sent
out. For example, for a 100 Mb input and 1 Gb output, the switch must wait
for the entire message to clock in at the slow rate before it can start outputting
the message at the high rate. Conversely for a 1 Gb/s input and 100 Mb/s
output, the entire packet is quickly read in at the faster rate, so then the output
can start sooner but at a lower rate.
