T3DSO2000A Manual. Page 83
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Clock Timeout – It is not necessary to specify the source and the threshold level for
the CS signal. The only parameter for the CS signal is the timeout Limit, which is the
minimum time that the clock signal must be held idle for before the oscilloscope
acquires valid data. This setting is suitable for the case where the CS signal is not
connected, or the number of oscilloscope channels is insufficient (such as two-channel
oscilloscopes).
The method of copying settings is the same as I2C signal settings. See " I2C Signal
Settings" for details.
Example:
Connect the data, CLK and ~CS signals of an SPI bus respectively to C1, C2 and C3.
Data width = 8-bit, Bit order = MSB, CS polarity = active low, and 12 data bytes are
transmitted in one frame.
In the SPI trigger signal menu, set the source and threshold of CLK, MISO and CS
signals, then copy the trigger settings to decoding. Adjust the timebase, so that there is
a falling edge on the CS signal shown in the screen:
When the CS type is set to Clock Timeout, turn on Cursor, measure the clock idle time
between frames as 300 μs, and measure the interval between clock pulses as 2.4 μs,
then set the timeout to a value between 2.4 and 300 μs. In this example it is set to 10 μs:
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