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SN32F760 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 149

Version 2.0

Call

bit (GC) in the ADR register is set.



A data byte has been received while the I2C is in the master

receiver mode.



A data byte has been received while the I2C is in the addressed

slave receiver mode.

HW will clear after issuing ACK automatically.

1

NACK

Assert NACK (HIGH level to SDA) flag.
0: No function
1: An NACK will be returned during the acknowledge clock pulse on SCLn

when



A data byte has been received while the I2C is in the master

receiver mode.

HW will clear after issuing NACK automatically.

R/W

0

0

Reserved

R

0

13.8.2 I2C n Status register (I2Cn_STAT) (n=0,1)

Address Offset: 0x04

Check this register when I2C interrupt occurs, and all status will be cleared automatically by writing I2Cn_CTRL or
I2Cn_TXDATA register.

While I2CIF =1, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended.
When SCL is HIGH, it is unaffected by the state of I2CIF.

Following events will trigger I2C interrupt if I2C interrupt is enabled in NVIC interrupt controller.



START/Repeat START condition



STOP condition



Timeout



Data byte transmitted or received



ACK Transmit or received



NACK Transmit or received

Bit

Name

Description

Attribute

Reset

31:16

Reserved

R

0

15

I2CIF

I2C Interrupt flag.
0: I2C status doesn’t change.
1: Read



I2C status changes.

Write



Clear this flag.

R/W

0

14:10

Reserved

R

0

9

TIMEOUT

Time-out status
0: No Timeout
1: Timeout

R

0

8

LOST_ARB

Lost arbitration
0: Not lost arbitration
1: Lost arbitration

R

0

7

SLV_TX_HIT

0: No matched slave address.
1: Slave address hit, and is called for TX in slave mode.

R

0

6

SLV_RX_HIT

0: No matched slave address.
1: Slave address hit, and is called for RX in slave mode.

R

0

5

MST

Master/Slave status
0: I2C is in Slave state.
1: I2C is in Master state.

R

0

4

START_DN

Start done status
0: No START bit.
1: MASTER mode



a START bit was issued.

SLAVE mode



a START bit was received.

R

0

3

STOP_DN

Stop done status
0: No STOP bit.
1: MASTER mode



a STOP condition was issued.

SLAVE mode



a STOP condition was received.

R

0

2

NACK_STAT

NACK done status

R

0

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Summary of Contents for SN32F755

Page 1: ...products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other...

Page 2: ...setting if ADC function is used 2 Update PLL recommend input output frequency setting table 1 5 2016 07 22 1 Fix typing errors 2 Add Notice HCLK MUST be equal or less than 24MHz during Flash program...

Page 3: ...ICK_LOAD 32 2 2 3 3 System Tick Timer Current Value register SYSTICK_VAL 33 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB 33 2 3 NESTED VECTORED INTERRUPT CONTROLLER NVIC 34 2 3 1...

Page 4: ...STAL CERAMIC 49 3 2 3 3 External Low speed ELS Clock 50 3 2 3 4 CRYSTAL 50 3 2 3 5 Bypass Mode 50 3 2 4 SYSTEM CLOCK SYSCLK SELECTION 51 3 2 5 CLOCK OUT CAPABITITY 51 3 3 SYSTEM CONTROL REGISTERS 0 52...

Page 5: ...4 6 OPERATION MODE COMPARSION TABLE 70 4 7 PMU REGISTERS 71 4 7 1 Backup registers 0 15 PMU_BKP0 15 71 4 7 2 Power Control register PMU_CTRL 71 4 7 3 I O Latch Control register 1 PMU_LATCHCTRL1 71 4...

Page 6: ...FPA_I2S 83 6 4 5 PFPA for CT16B0 register PFPA_CT16B0 84 6 4 6 PFPA for CT16B1 register PFPA_CT16B1 85 6 4 7 PFPA for CT16B2 register PFPA_CT16B2 86 6 4 8 PFPA for CT32B0 register PFPA_CT32B0 86 6 4 9...

Page 7: ...TRL n 0 1 2 107 8 7 9 CT16Bn Capture 0 register CT16Bn_CAP0 n 0 1 2 107 8 7 10 CT16Bn External Match register CT16Bn_EM n 0 1 2 108 8 7 11 CT16Bn PWM Control register CT16Bn_PWMCTRL n 0 1 2 108 8 7 12...

Page 8: ...G 127 10 3 2 Watchdog Clock Source register WDT_CLKSOURCE 127 10 3 3 Watchdog Timer Constant register WDT_TC 127 10 3 4 Watchdog Feed register WDT_FEED 128 1 1 11 1 1 REAL TIME CLOCK RTC 129 11 1 OVER...

Page 9: ...12 6 7 SSP n Interrupt Clear register SSPn_IC n 0 1 142 12 6 8 SSP n Data register SSPn_DATA n 0 1 142 12 6 9 SSP n Data Fetch register SSPn_DF n 0 1 142 1 1 13 3 3 I2C 143 13 1 OVERVIEW 143 13 2 FEA...

Page 10: ...156 14 5 5 RS485 EIA 485 OUTPUT INVERSION 156 14 5 6 RS485 EIA 485 FRAME STRUCTURE 156 14 6 BAUD RATE CALCULATION 156 14 7 MODEM CONTROL MC 158 14 7 1 AUTO RTS 158 14 7 2 AUTO CTS 159 14 8 AUTO BAUD...

Page 11: ...lue register USARTn_RS485DLYV n 0 1 173 14 11 21 USART n Synchronous Mode Control Register USARTn_SYNCCTRL n 0 1 174 1 1 15 5 5 I2S 175 15 1 OVERVIEW 175 15 2 FEATURES 175 15 3 PIN DESCRIPTION 175 15...

Page 12: ...r Control register LCD_FCC 196 16 9 6 LCD Raw Interrupt Status register LCD_RIS 197 16 9 7 LCD SEG Memory register 0 LCD_SEGM0 197 16 9 8 LCD SEG Memory register 1 LCD_SEGM1 198 16 9 9 LCD SEG Memory...

Page 13: ...DEBUG RECOVERY 206 18 4 3 INTERNAL PULL UP DOWN RESISTORS on SWD PINS 207 1 1 19 9 9 DEVELOPMENT TOOL 208 19 1 SN LINK V3 209 19 2 SN32F760 STARTER KIT 210 2 2 20 0 0 ELECTRICAL CHARACTERISTIC 212 20...

Page 14: ...ereo audio data clock source and divider supported MSB justified data format supported and can operate as either master or slave System tick timer 24 bit timer System clocks The system tick timer cloc...

Page 15: ...itx3 USARTx1 UARTx1 2 2 1 21 8CH 4x18 42 LQFP48 SN32F766J 64KB 8KB 4KB 50 MHz 16 bitx3 32 bitx3 USARTx1 UARTx1 2 2 1 21 7CH 4x17 40 QFN46 SN32F765J 64KB 8KB 4KB 50 MHz 16 bitx3 32 bitx3 UARTx2 2 2 21...

Page 16: ...S POWER CONTROL SYSTEM FUNCTIONS SPI1 I2C0 USART 0 SPI0 USART 1 POWER REGULATOR 1 ILRC 32KHz IHRC 12MHz LVD Clocks Controls AHB LITE BUS AHB TO APB BRIDGE APB BUS RTC GPIO VCORE VDD 1 8V 5 5V I2C1 SCL...

Page 17: ...PCLK AHB clock for ADC ADCCLKEN ADC register block ADC clock source I2S Clock Prescaler 1 2 3 4 8 16 I2S_PCLK AHB clock for I2S I2SCLKEN I2S register block I2S clock source I2Cn Clock Prescaler 1 2 4...

Page 18: ...56 P3 2 SEG4 P2 14 6 55 P1 7 V2 P2 15 7 54 P1 6 V3 AIN5 P2 5 8 53 P1 8 CL AIN6 P2 6 9 52 P1 9 CL AIN7 P2 7 10 SN32F769F SN32F759F 51 VSS AIN8 P2 8 11 50 P3 1 SEG3 AIN9 P2 9 12 49 P3 0 SEG2 AIN10 P2 10...

Page 19: ...P1 9 CL P2 15 7 SN32F768F SN32F758F 42 P3 1 SEG3 AIN5 P2 5 8 41 P3 0 SEG2 AIN6 P2 6 9 40 P1 15 SEG1 AIN10 P2 10 10 39 P1 14 SEG0 AIN11 P2 11 11 38 P1 13 COM3 AIN12 P2 12 12 37 P1 12 COM2 AIN13 P2 13...

Page 20: ...G4 AIN3 P2 3 4 33 P1 7 V2 AIN4 P2 4 5 SN32F767F SN32F757F 32 P1 6 V3 P2 14 6 31 P3 1 SEG3 P2 15 7 30 P3 0 SEG2 AIN5 P2 5 8 29 P1 13 COM3 AIN6 P2 6 9 28 P1 12 COM2 AIN7 P2 7 10 27 P1 11 COM1 AVSS 11 26...

Page 21: ...1 P1 7 V2 BOOT AIN2 P2 2 3 SN32F766J SN32F756J 30 P1 6 V3 AIN3 P2 3 4 29 P3 1 SEG3 AIN4 P2 4 5 28 P3 0 SEG2 P2 14 6 27 P1 13 COM3 P2 15 7 26 P1 12 COM2 AIN5 P2 5 8 25 P1 11 COM1 AIN6 P2 6 9 24 P1 10 C...

Page 22: ...28 27 26 25 LXTALOUT P3 15 1 24 VDD AIN0 P2 0 2 23 P3 9 AIN1 P2 1 3 SN32F765J SN32F755J 22 P3 6 BOOT AIN2 P2 2 4 21 P3 3 P2 14 5 20 P3 2 P2 15 6 19 P1 11 AIN7 P2 7 7 18 P1 10 AVSS 8 33 VSS 17 VDD12 9...

Page 23: ...irection pin Schmitt trigger structure and built in pull up pull down resisters as input mode P0 8 SWCLK I O P0 8 Port 0 8 bi direction pin Schmitt trigger structure and built in pull up pull down res...

Page 24: ...resisters as input mode LXTALIN External low speed X tal input pin P3 15 LXTALOUT I O P3 15 Port 3 15 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode...

Page 25: ...SCL1 I2SBCLK CT16B1_PWM2 CT16B1_PWM0 CT32B0_PWM2 P1 10 COM0 MISO1 I2SWS CT16B1_PWM3 CT16B1_PWM1 CT32B1_PWM1 P1 11 COM1 SEL0 SCK1 CT16B1_CAP0 CT16B2_PWM1 CT32B0_PWM1 P1 12 COM2 SCK0 CT16B0_PWM0 CT16B0...

Page 26: ...CT32B2_PWM1 CT32B2_CAP0 P3 8 SEG10 UTXD1 I2SDOUT MOSI1 CT16B1_PWM2 CT32B0_PWM1 CT32B1_CAP0 P3 9 SEG11 I2SDIN MISO1 SCL0 CT16B1_PWM1 CT32B0_PWM0 CT32B1_PWM3 CT32B0_CAP0 P3 10 RESET UTXD0 UTXD1 SEL0 CT1...

Page 27: ...TECHNOLOGY CO LTD Page 27 Version 2 0 than VDD user should manually force to set the I O port P1 6 and P1 7 as input pull down state in case of internal power collision 5 VDD1 VLCD1 VDD2 VLCD2 VDD3 V...

Page 28: ...t Bus GPIOPn_MODE RPD GPIOn_CFG GPIOPn_MODE Specific Input Bus Specific Input Function Control Bit Specific Output Function Control Bit Some specific functions switch I O direction directly not throug...

Page 29: ...Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn_MODE register Analog IP Input Terminal Bi direction I O Pin Shared with Specific Analog Out...

Page 30: ...00 Reserved 0x4002 8000 0x4002 6000 Reserved Reserved I2C0 0x4004 4000 0x4004 6000 0x4004 8000 GPIO 2 GPIO 3 GPIO 0 GPIO 1 Reserved 0x4008 0000 0xE000 0000 0xE010 0000 0xE000 ED00 0xE000 F000 Reserved...

Page 31: ...fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The block...

Page 32: ...OURCE Selects the SysTick timer clock source 0 reference clock 1 system clock Fixed R 1 1 TICKINT System Tick interrupt enable 0 Disable the System Tick interrupt 1 Enable the System Tick interrupt th...

Page 33: ...W 0x7E7F35 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB Address 0xE000 E01C Refer to Cortex M0 Spec Bit Name Description Attribute Reset 31 NOREF Indicates the reference clock to...

Page 34: ...00 1 3 Reset Reset 0x0000 0004 2 2 NMI_Handler Non maskable interrupt 0x0000 0008 3 1 HardFault_Handler All class of fault 0x0000 000C 4 10 Reserved Reserved Reserved 11 Settable SVCCalll 0x0000 002C...

Page 35: ...0x0000 00AC 44 Settable IRQ28 P3IRQ GPIO interrupt status of port 3 0x0000 00B0 45 Settable IRQ29 P2IRQ GPIO interrupt status of port 2 0x0000 00B4 46 Settable IRQ30 P1IRQ GPIO interrupt status of po...

Page 36: ...bit does not affect the active state of the corresponding interrupt Bit Name Description Attribute Reset 31 0 CLRPEND 31 0 Interrupt clear pending bits Write 0 No effect 1 Removes pending state of an...

Page 37: ...writing 255 to a priority register saves value 192 to the register R W 0 2 4 APPLICATION INTERRUPT AND RESET CONTROL AIRC Address 0xE000 ED0C Refer to Cortex M0 Spec The entire MCU including the core...

Page 38: ...oller SONiX TECHNOLOGY CO LTD Page 38 Version 2 0 2 5 CODE OPTION TABLE Address 0x1FFF 2000 Bit Name Description Attribute Reset 31 16 Code Security 15 0 Code Security 0xFFFF CS0 0x5A5A CS1 0xA5A5 CS2...

Page 39: ...ster LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with th...

Page 40: ...but the crystal type is longer Under client terminal application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD VS...

Page 41: ...gram is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROW...

Page 42: ...minimum operating voltage which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic s...

Page 43: ...condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in rese...

Page 44: ...e basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a...

Page 45: ...Zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C termin...

Page 46: ...Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes re...

Page 47: ...oscillator on chip PLL circuit The low speed clock is generated from on chip low speed RC oscillator circuit ILRC 16 KHz 3 2 1 INTERNAL RC CLOCK SOURCE 3 2 1 1 Internal High speed RC Oscillator IHRC T...

Page 48: ...phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock The PLL settling time is 100 s PFD LPF VCO DIV M DIV P Fclkout Fvco Fclkin DIV F...

Page 49: ...ces are driven by XIN XOUT pins For high normal low frequency the driving currents are different MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as po...

Page 50: ...ns The 32768 crystal and 10pF capacitor must be as near as possible to MCU The ELS crystal is switched on and off using the ELSEN bit in Analog Block Control register SYS0_ANBCTRL Note Connect the Cry...

Page 51: ...lock source to another occurs only if the target clock source is ready clock stable after startup delay or PLL locked If a clock source which is not yet ready is selected the switch will occur when th...

Page 52: ...3 Reserved R 0 2 ELSEN External low speed oscillator enable 0 Disable External 32 768 KHz oscillator 1 Enable External 32 768 KHz oscillator R W 0 1 Reserved R 0 0 IHRCEN Internal high speed clock en...

Page 53: ...ps Fclkout Fclkin V V V V V V V V V V V V 44MHz 48MHz 16MHz 22MHz 16MHz 12MHz 12MHz 20MHz 30MHz 40MHz 22MHz 24MHz 25MHz 10MHz 10MHz 50MHz 24MHz 25MHz 32MHz 36MHz 3 3 2 1 RECOMMEND FREQUENCY SETTING F...

Page 54: ...7 Reserved R 0 6 4 SYSCLKST 2 0 System clock switch status Set and cleared by HW to indicate which clock source is used as system clock 000 IHRC is used as system clock 001 ILRC is used as system cloc...

Page 55: ...n occurred R W 0 2 LVDRSTF LVD reset flag Set by HW when a LVD reset occurs 0 Read No LVD reset occurred Write Clear this bit 1 LVD reset occurred R W 0 1 WDTRSTF WDT reset flag Set by HW when a WDT r...

Page 56: ...in Control register SYS0_EXRSTCTRL Address Offset 0x1C Bit Name Description Attribute Reset 31 1 Reserved R 0 0 RESETDIS External RESET pin disable bit 0 Enable external RESET pin P3 10 acts as RESET...

Page 57: ...Clock output source 000 Disable 001 ILRC clock 010 ELS clock 100 HCLK 101 IHRC clock 110 EHS clock 111 PLL clock output R W 0 27 25 Reserved R 0 24 WDTCLKEN Enables clock for WDT 0 Disable 1 Enable R...

Page 58: ...DCLKEN Enables clock for LCD 0 Disable 1 Enable R W 0 1 Reserved R 0 0 GPIOCLKEN Enables clock for GPIO 0 Disable 1 Enable R W 1 3 4 2 APB Clock Prescale register 0 SYS1_APBCP0 Address Offset 0x04 Not...

Page 59: ...R 0 10 8 CT32B0PRE 2 0 CT32B0 clock source prescaler 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved R W 0 7 Reserved R 0 6 4 CT16B1PRE 2 0 CT16B1 clock source prescaler 000 HC...

Page 60: ...lock source 4 011 WDT_PCLK WDT clock source 8 100 WDT_PCLK WDT clock source 16 101 WDT_PCLK WDT clock source 32 Other Reserved R W 0 19 15 Reserved R 0 14 12 I2SPRE 2 0 I2S clock source prescaler 000...

Page 61: ...Other Reserved R W 0 3 4 5 Peripheral Reset register SYS1_PRST Address Offset 0x10 All bits are cleared by HW automatically after setting as 1 Bit Name Description Attribute Reset 31 25 Reserved R 0 2...

Page 62: ...CT32B0RST CT32B0 reset 0 No effect 1 Reset CT32B0 R W 0 7 CT16B2RST CT16B2 reset 0 No effect 1 Reset CT16B2 R W 0 6 CT16B1RST CT16B1 reset 0 No effect 1 Reset CT16B1 R W 0 5 CT16B0RST CT16B0 reset 0 N...

Page 63: ...ng Hard Fault since FW shall be able to handle this case Bit Name Description Attribute Reset 31 0 Divisor 31 0 Unsigned integer Divisor R W 0 3 4 8 Divider Quotient register SYS1_QUOTIENT Address Off...

Page 64: ...4 10 Divider Control register SYS1_DIVCTRL Address Offset 0x30 Bit Name Description Attribute Reset 31 1 Reserved R 0 0 DIVS Divider start control bit 0 Divider stops finishes operation 1 Start to exe...

Page 65: ...power down mode The PMU_CTRL register controls which mode is desired The CPU clock rate may also be controlled as needed by changing clock sources re configuring PLL values and or altering the system...

Page 66: ...and internal SRAM values are maintained and the logic levels of the pins remain static All GPIO pins are served as wakeup pins The user must program the GPIO registers for each pin to set the appropri...

Page 67: ...mode 1 Disable analog IP ADC LCD HXTAL LXTAL External reset SWD 2 Setup the desired GPIO status of all GPIO pins The DPDWAKEUP pins which are used to wake up MCU shall be set as input pull up and keep...

Page 68: ...illator clocks and 32 internal high speed oscillator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from Sleep mode s...

Page 69: ...sleep mode Sleep mode Wake up condition Interrupt Wake up condition GPIO Wakeup RTC interrupt LCD interrupt Wake up condition Pulling any of the DPDWAKEUP pins LOW Reset condition One of reset trigge...

Page 70: ...sh ROM Enable Disable Disable OFF RAM Enable Maintain Maintain OFF ADC By ADENB Disable Disable LVD By LVDEN Disable OFF LCD By LCDENB OFF RTC By RTCEN By RTCEN OFF Peripherals By Enable bit of each p...

Page 71: ...ts whether one of the ARM Cortex M0 controlled power down modes Sleep mode or Deep sleep mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep modes and Deep power...

Page 72: ...function R W 0 4 7 4 I O Latch Control register 2 PMU_LATCHCTRL2 Address Offset 0x48 Bit Name Description Attribute Reset 31 16 LATCHKEY Latch register key Read as 0 When writing to the register you...

Page 73: ...nal pull up pull down resistor Most of the I O pins are mixed with analog pins and special function pins 5 2 GPIO MODE All GPIO pins are inputs and floating by default The MODE bits in the GPIOn_CFG n...

Page 74: ...ribute Reset 31 16 CURRENT 15 0 Driving Sinking current selection x 0 to 15 0 Typical 10mA 1 Typical 20mA R W 0 15 0 MODE 15 0 Selects pin x as input or output x 0 to 15 0 Pn x is configured as input...

Page 75: ...resistor enabled 11 Repeater mode R W 10b 15 14 CFG7 1 0 Configuration of Pn 7 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater...

Page 76: ...Pn x is controlled through register GPIOn_IEV 1 Both edges on Pn x trigger an interrupt R W 0 5 3 6 GPIO Port n Interrupt Event register GPIOn_IEV n 0 1 2 3 Address offset 0x14 Bit Name Description At...

Page 77: ...terrupt flag on pin x to be cleared x 0 to 15 0 No effect 1 Clear interrupt flag on Pn x W 0 5 3 10 GPIO Port n Bits Set Operation register GPIOn_BSET n 0 1 2 3 Address offset 0x24 In order for SW to...

Page 78: ...n pin Open drain pin MCU1 Pull up Resistor The external pull up resistor is necessary The digital output function of I O only supports sink current capability so the open drain output high is driven b...

Page 79: ...SCK0 P0 4 P0 11 P0 13 P1 4 P1 12 P3 2 P3 6 P3 11 P2 3 P2 14 SEL0 P0 5 P0 10 P0 12 P1 5 P1 11 P3 1 P3 5 P3 10 P2 0 P2 15 MISO0 P0 2 P0 0 P0 6 P0 15 P1 0 P1 14 P3 3 P3 15 P2 1 P2 12 MOSI0 P0 3 P0 1 P0 7...

Page 80: ...P2 14 PWM1 P3 8 P0 8 P0 14 P1 5 P1 11 P3 14 P2 4 P2 13 PWM2 P1 14 P0 5 P0 9 P1 9 P3 7 P3 13 P2 0 P2 11 PWM3 P1 2 P0 3 P0 7 P0 15 P1 12 P3 4 P2 2 P2 12 CT32B1 CAP0 P1 3 P0 2 P0 8 P0 15 P1 6 P3 8 P2 4...

Page 81: ...o be assigned as UTXD0 0000 P0 1 0001 P0 5 0010 P1 2 0011 P3 1 0100 P3 2 0101 P3 4 0110 P3 10 0111 P3 15 Other Reserved R W 0000b 6 4 2 PFPA for I2C register PFPA_I2C Address offset 0x04 Bit Name Desc...

Page 82: ...0 P3 6 0001 P0 2 0010 P0 13 0011 P1 0 0100 P1 4 0101 P1 7 0110 P1 14 0111 P3 11 1000 P2 1 1001 P2 14 Other Reserved R W 0000b 27 24 SCK1 3 0 Pin to be assigned as SCK1 0000 P3 7 0001 P0 7 0010 P0 14 0...

Page 83: ...01 P2 14 Other Reserved R W 0000b 7 4 MOSI0 3 0 Pin to be assigned as MOSI0 0000 P0 3 0001 P0 1 0010 P0 7 0011 P0 14 0100 P1 1 0101 P1 15 0110 P3 4 0111 P3 14 1000 P2 2 1001 P2 13 Other Reserved R W 0...

Page 84: ...0000b 3 0 MCLK 3 0 Pin to be assigned as I2SMCLK 0000 P3 2 0001 P0 12 0010 P1 8 0011 P3 7 0100 P2 2 0101 P2 6 Other Reserved R W 0000b 6 4 5 PFPA for CT16B0 register PFPA_CT16B0 Address offset 0x10 B...

Page 85: ...2 PWM2 3 0 Pin to be assigned as CT16B1_PWM2 0000 P1 9 0001 P0 6 0010 P0 15 0011 P1 2 0100 P1 14 0101 P3 8 0110 P2 3 0111 P2 7 Other Reserved R W 0000b 11 8 PWM1 3 0 Pin to be assigned as CT16B1_PWM1...

Page 86: ...11 0100 P3 5 0101 P3 15 0110 P2 1 0111 P2 6 Other Reserved R W 0000b 7 4 PWM0 3 0 Pin to be assigned as CT16B2_PWM0 0000 P3 5 0001 P0 2 0010 P0 14 0011 P1 4 0100 P3 1 0101 P3 10 0110 P2 5 0111 P2 9 O...

Page 87: ...001 P0 4 0010 P0 11 0011 P1 8 0100 P1 14 0101 P3 9 0110 P2 3 0111 P2 14 Other Reserved R W 0000b 3 0 CAP0 3 0 Pin to be assigned as CT32B0_CAP0 0000 P3 9 0001 P0 0 0010 P0 9 0011 P1 1 0100 P3 1 0101 P...

Page 88: ...AP0 0000 P1 3 0001 P0 2 0010 P0 8 0011 P0 15 0100 P1 6 0101 P3 8 0110 P2 4 0111 P2 10 Other Reserved R W 0000b 6 4 10 PFPA for CT32B2 register PFPA_CT32B2 Address offset 0x28 Bit Name Description Attr...

Page 89: ...Reserved 7 4 PWM0 3 0 Pin to be assigned as CT32B2_PWM0 0000 P0 13 0001 P0 3 0010 P0 8 0011 P1 1 0100 P1 7 0101 P1 15 0110 P2 11 0111 P2 15 Other Reserved R W 0000b 3 0 CAP0 3 0 Pin to be assigned as...

Page 90: ...DC channel the analog signal inputs to ADC engine The ADC reference high voltage includes two source one is internal Vdd AVREFHSEL 0 and the other one is external reference voltage input pin from P2 0...

Page 91: ...nverting rate If the ADC converting time is slower than analog signal variation rate the ADC result would be error So to select a correct ADC clock rate and ADC resolution to decide a right ADC conver...

Page 92: ...pin It is necessary to set P2 0 as input mode without pull up resistor Step 3 Select the ADC input pin by CHS 3 0 and enable ADC global input When one AIN pin is selected to be analog signal input pi...

Page 93: ...ure sensor is enabled When not in use this sensor can be put in power down mode if TSENB 0 Note The Temperature Sensor was just a reference data not real air temperature For precision application plea...

Page 94: ...L ADC high reference voltage source select bit 0 Internal VDD P2 0 is GPIO or AIN0 pin 1 Enable external reference voltage from P2 0 R W 0 11 ADENB ADC Enable bit 0 Disable 1 Enable R W 0 10 8 ADCKS 2...

Page 95: ...ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 8 bit O O O O O O O O X X X X 9 bit O O O O O O O O O X X X 10 bit O O O O O O O O O O X X 11 bit O O O O O O O O O O O X 12 bit O O O O O O O O O O O O O Selected X...

Page 96: ...t is not desirable at the end of each conversion for some A D channels Bit Name Description Attribute Reset 31 15 Reserved R 0 14 0 IE 14 0 These bits allow control over which A D channels generate in...

Page 97: ...lue when an input signal transitions A capture event may also optionally generate an interrupt The timer and prescaler may be configured to be cleared on a designated capture event This feature permit...

Page 98: ...NiX TECHNOLOGY CO LTD Page 98 Version 2 0 8 4 BLOCK DIAGRAM CT16Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC PRE TC CEN MRx Interrupt MRxSTOP STOP CRST CRST RESET RESET MRxRST CAP0 CAP0EN CAP0FE CAP0RE CA...

Page 99: ...ull length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK CT16Bn_PC CT16Bn_TC TC Reset Interrupt 2...

Page 100: ...g mode The CT16Bn_PRE register is set to 0 and the CT16Bn_MR3 register is set to 54 After TC reaches 0 the timer count is reset and loaded from the value of CT16Bn_MR3 PCLK CT16Bn_TC 4 3 2 1 0 54 53 5...

Page 101: ...PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 If a matc...

Page 102: ...ntrolled PWM outputs go HIGH at the beginning of each PWM cycle timer is set to zero unless their match value in CT16Bn_MR0 3 registers is equal to zero 2 Each PWM output will go LOW when its match va...

Page 103: ...atch register is set to zero then the PWM output will go LOW the first time the timer goes back to zero and will stay LOW continuously CT16Bn_MR0 60 0 100 TC resets 60 25 CT16Bn_MR1 25 PWM0 PWM1 CT16B...

Page 104: ...er Reserved R W 000b 3 2 Reserved R 0 1 CRST Counter Reset 0 Disable counter reset 1 Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK This is cleared by...

Page 105: ...nting When Counter Mode is chosen as a mode of operation the CAP input selected by the CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP in...

Page 106: ...enerating an interrupt based on CM 2 0 when MR3 matches the value in the TC 0 Disable 1 Enable R W 0 8 MR2STOP Stop MR2 TC and PC will stop and CEN bit will be cleared if MR2 matches TC 0 Disable 1 En...

Page 107: ...a capture event for both edges Note HW will switch I O Configuration directly when CAP0EN 1 Bit Name Description Attribute Reset 31 4 Reserved R 0 3 CAP0EN Capture 0 function enable bit 0 Disable 1 E...

Page 108: ...are equal this bit will act according to EMC0 bits and also drive the state of CT16Bn_PWM0 output R W 0 8 7 11 CT16Bn PWM Control register CT16Bn_PWMCTRL n 0 1 2 Address Offset 0x34 The PWM Control r...

Page 109: ...Timer Raw Interrupt Status register CT16Bn_RIS n 0 1 2 Address Offset 0x38 This register indicates the raw status for Timer PWM interrupts A Timer PWM interrupt is sent to the interrupt controller if...

Page 110: ...pt Clear register CT16Bn_IC n 0 1 2 Address Offset 0x3C Bit Name Description Attribute Reset 31 5 Reserved R 0 4 CAP0IC 0 No effect 1 Clear CAP0IF bit W 0 3 MR3IC 0 No effect 1 Clear MR3IF bit W 0 2 M...

Page 111: ...alue when an input signal transitions A capture event may also optionally generate an interrupt 4 The timer and prescaler may be configured to be cleared on a designated capture event This feature per...

Page 112: ...iX TECHNOLOGY CO LTD Page 112 Version 2 0 9 4 BLOCK DIAGRAM CT32Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC PRE TC CEN MRx Interrupt MRxSTOP STOP CRST CRST RESET RESET MRxRST CAP0 CAP0EN CAP0FE CAP0RE CA...

Page 113: ...ll length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK CT32Bn_PC CT32Bn_TC TC Reset Interrupt 2 0...

Page 114: ...g mode The CT32Bn_PRE register is set to 0 and the CT32Bn_MR3 register is set to 54 After TC reaches 0 the timer count is reset and loaded from the value of CT32Bn_MR3 PCLK CT32Bn_TC 4 3 2 1 0 54 53 5...

Page 115: ...M output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 If a match...

Page 116: ...ntrolled PWM outputs go HIGH at the beginning of each PWM cycle timer is set to zero unless their match value in CT32Bn_MR0 3 registers is equal to zero 2 Each PWM output will go LOW when its match va...

Page 117: ...atch register is set to zero then the PWM output will go LOW the first time the timer goes back to zero and will stay LOW continuously CT32Bn_MR0 60 0 100 TC resets 60 25 CT32Bn_MR1 25 PWM0 PWM1 CT32B...

Page 118: ...ting and down counting period Other Reserved R W 000b 3 2 Reserved R 0 1 CRST Counter Reset 0 Disable counter reset 1 Timer Counter is synchronously reset on the next positive edge of PCLK This is cle...

Page 119: ...lected by CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge e...

Page 120: ...IE Enable generating an interrupt based on CM 2 0 when MR2 matches the value in the TC 0 Disable 1 Enable R W 0 5 MR1STOP Stop MR1 TC will stop and CEN bit will be cleared if MR1 matches TC 0 Disable...

Page 121: ...2Bn_CAP0 will cause CAP0 to be loaded with the contents of TC 0 Disable 1 Enable R W 0 0 CAP0RE Capture on CT32Bn_CAP0 rising edge a sequence of 0 then 1 on CT32Bn_CAP0 will cause CAP0 to be loaded wi...

Page 122: ...RL n 0 1 2 Address Offset 0x34 The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match out...

Page 123: ...PWM0 is controlled by EM0 1 PWM mode is enabled for CT32Bn_PWM0 R W 0 9 7 12 CT32Bn Timer Raw Interrupt Status register CT32Bn_RIS n 0 1 2 Address Offset 0x38 This register indicates the raw status fo...

Page 124: ...pt Clear register CT32Bn_IC n 0 1 2 Address Offset 0x3C Bit Name Description Attribute Reset 31 5 Reserved R 0 4 CAP0IC 0 No effect 1 Clear CAP0IF bit W 0 3 MR3IC 0 No effect 1 Clear MR3IF bit W 0 2 M...

Page 125: ...he Watchdog and setup the Watchdog timer operating mode in WDT_CFG register 5 The Watchdog should be fed again by writing 0x55AA to WDT_FEED register before the Watchdog counter underflows to prevent...

Page 126: ...o Controller SONiX TECHNOLOGY CO LTD Page 126 Version 2 0 10 2 BLOCK DIAGRAM WDT_FEED WDT_TC 128 8 bit Down Counter WDINT WDTIE WDTEN WDT_PCLK Feed OK Feed Watchdog Enable Counter Reload Counter under...

Page 127: ...g timeout will cause a chip reset Watchdog reset mode Watchdog counter underflow will reset the MCU and will clear the WDINT flag 1 Watchdog timeout will cause an interrupt Watchdog interrupt mode R W...

Page 128: ...value TC 7 0 1 0000 0000 Timer constant 1 0000 0001 Timer constant 2 1111 1110 Timer constant 255 1111 1111 Timer constant 256 R W 0xFF 10 3 4 Watchdog Feed register WDT_FEED Address Offset 0x0C Bit N...

Page 129: ...to detect when the internal programmable counter rolls over to zero 11 3 FUNCTIONAL DESCRIPTION 11 3 1 INTRODUCTION RTC core includes a 20 bit preload value RTC SECCNTV Every TR_CLK period the RTC ge...

Page 130: ...is configured with RTC_SECCNTV 3 RTC_ALMCNTV 0x1000 RTC_PCLK 0x0 Cleared by SW r RTC_SECCNT 0x1 0x2 0x3 RTC_SECIF 0x0 0x1 0x2 0x3 0x0 0x0 RTC_ALMCNT 0x1 0x2 0x0 0x1 0x2 0x3 0x0 0x9FF 0x1000 0x3 0x1001...

Page 131: ...ECHNOLOGY CO LTD Page 131 Version 2 0 11 4 BLOCK DIAGRAM RTC_SECCNT RTC_ALMCNT SRC_SEL ELS_XTAL EHS_XTAL 128 ILRC SEC_CNT_CLK RTC_SECCNTV RTC_ALMCNTV SECOND SECIF ALMIF OVFIF RTCEN SECIE SECOND Interr...

Page 132: ...ll disable RTC RTCEN 0 when changing the value of this register Bit Name Description Attribute Reset 31 2 Reserved R 0 1 0 CLKSEL 1 0 RTC clock source selection HW will reset SEC_CNT and ALM_CNT when...

Page 133: ...fset 0x10 Bit Name Description Attribute Reset 31 3 Reserved R 0 2 OVFIC 0 No effect 1 Clear OVFIF bit W 0 1 ALMIC 0 No effect 1 Clear ALMIF bit W 0 0 SECIC 0 No effect 1 Clear SECIF bit W 0 11 5 6 RT...

Page 134: ...alarm counter reload value Update this register will reset ALMCNT The zero value is not recommended and will be replaced with default value 0xFFFFFFFF by HW R W 0xFFFFFFFF 11 5 9 RTC Alarm Count regis...

Page 135: ...FEATURES Compatible with Motorola SPI and 4 wire TI SSI bus Synchronous Serial Communication Supports master or slave operation 8 frame FIFO for both transmitter and receiver 4 bit to 16 bit frame Max...

Page 136: ...control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA clock phase bit controls the phase of the clock on which data is sampled When CPHA 1...

Page 137: ...o the serial shift register of the shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Both the SSP hardware and the off chip...

Page 138: ...CS DATA F0 msb F0 F0 F0 lsb F1 msb F1 F1 F1 lsb SCK SCK SCK SCK CPOL 0 CPHA 1 CPOL 1 CPHA 0 CPOL 1 CPHA 1 CPOL 0 CPHA 0 SPI TI 12 5 AUTO SEL The Auto SEL function is disabled SELDIS 1 by default HW do...

Page 139: ...000b 14 12 TXFIFOTH 2 0 TX FIFO Threshold level 000 TX FIFO threshold level 0 001 TX FIFO threshold level 1 111 TX FIFO threshold level 7 R W 000b 11 8 DL 3 0 Data length DL 3 0 1 0000 0001 Reversed...

Page 140: ...tion bit 0 MSB transmit first 1 LSB transmit first R W 0 12 6 3 SSP n Clock Divider register SSPn_CLKDIV n 0 1 Address Offset 0x08 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DIV 7 0 SS...

Page 141: ...atus for each interrupt condition regardless of whether or not the interrupt is enabled in SSPn_IE register This register indicates the status for SSP control raw interrupts An SSP interrupt is sent t...

Page 142: ...X_FULL 0 in SSPn_STAT register TX FIFO is not full If the TX FIFO was previously empty and the SSP controller is not busy on the bus transmission of the data will begin immediately Otherwise the data...

Page 143: ...he master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial...

Page 144: ...of slave address I2C bus can be used for test and diagnostic purposes Generation and detection of 7 bit 10 bit addressing and General Call 13 3 PIN DESCRIPTION Pin Name Type Description GPIO Configur...

Page 145: ...4 D4 5 D3 6 D2 7 D1 P 9 D6 ACK_ 9 8 D0 D0 Write 1 to ACK bit Start Acknowledge sequence ACK from Master Receiving Data from Slave ACK_ is not sent Write 1 to STO bit Master terminal transfer Data shif...

Page 146: ...7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R W 0 ACK_ 1 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL Transmission Data R W 1 D7 13 6 2 SLAVE RECEIVER MODE S Receiving Address ACK_ 1 A7 2 A6 3 A5 4 A4 5 A3...

Page 147: ...ve on the bus which was actually addressed by the master Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus 13 7 2 LOSS of ARBIT...

Page 148: ...interface is in master mode and transmits a START condition thereafter If the I2C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN sha...

Page 149: ...t is unaffected by the state of I2CIF Following events will trigger I2C interrupt if I2C interrupt is enabled in NVIC interrupt controller START Repeat START condition STOP condition Timeout Data byte...

Page 150: ...Offset 0x0C Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DATA 7 0 Contains the data received Read this register when RX_DN 1 R 0x00 13 8 5 I2C n Slave Address 0 register I2Cn_SLVADDR0 n...

Page 151: ...cycle When I2C timeout occurs the I2C transfer will return to IDLE state and issue a TO interrupt to inform user That means SCL SDA will be released by HW after timeout User can issue a STOP after ti...

Page 152: ...e generated when the address matches one of the values in I2Cn_SLVADDR0 3 register 1 If I2C is in monitor mode an interrupt will be generated on ANY address received This will enable the part to monit...

Page 153: ...onous transmission 16 byte receive and transmit FIFOs Register locations conform to 16550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Software or...

Page 154: ...ontroller SONiX TECHNOLOGY CO LTD Page 154 Version 2 0 14 4 BLOCK DIAGRAM UART Baud Rate Generator RX DLL DLM USARTn_RB RSR TX USARTn_TH TSR UTXD URXD APB MODEM MS MC UCTS URTS SCR INTERRUPT USARTn_IE...

Page 155: ...and stored in the RXFIFO regardless of whether they are data or address When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to...

Page 156: ...driven LOW when the transmitter has data waiting to be sent The direction control pin will be driven to logic 0 driven High once the last bit of data has been transmitted 14 5 6 RS485 EIA 485 FRAME ST...

Page 157: ...1 3 4 Sampled values 7 16 7 16 6 16 Sampling Clock 1 BIT TIME 2 6 7 5 9 10 8 12 13 11 15 16 14 If the USARTn_FD register value does not comply with these two requests then the fractional divider outp...

Page 158: ...ed to a high value It is possible that the sending USART sends an additional byte after the trigger level is reached assuming the sending USART has another byte to send because it might not recognize...

Page 159: ...8 AUTO BAUD FLOW 14 8 1 AUTO BAUD The USART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes command If enabled the auto baud feature will measure the b...

Page 160: ...ill execute the following phases 1 On START bit setting the baud rate measurement counter is reset and the RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on URXD pin t...

Page 161: ...that is not synchronous with the data bit rate The USCLK pin may not be adequate for most asynchronous cards since it will output synchronously with the data and the data bit rate SW must use timers...

Page 162: ...the USART transmitter clock No clock pulses are sent to the SCLK pin during start bit and stop bit The CPOL bit in USARTn_CTRL register allows the user to select the clock polarity and the CPHA bit a...

Page 163: ...Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 163 Version 2 0 CPOL CPHA SCLK Idle Status Diagrams 0 1 Low LSB bit1 MSB 1 1 High LSB bit1 MSB 0 0 Low Next data LSB bit1 MSB 1 0 High Next...

Page 164: ...er is the top byte of the USART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Acce...

Page 165: ...interrupt can be read from TEMT bit in USARTn_LS register 0 Disable 1 Enable R W 0 3 MSIE Modem Status interrupt enable bit The components of this interrupt can be read from USARTn_MS register 0 Disa...

Page 166: ..._II 9 8 are set by the auto baud function and signal a time out or end of auto baud condition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Co...

Page 167: ...s bit causes the USART to issue THRE interrupt to if THREIE 1 THRE 1 when a character is transferred from the THR into the TSR The bit is reset to logic 0 concurrently with the loading of the Transmit...

Page 168: ...aracters must be written before an interrupt is activated 00 Trigger level 0 1 character 01 Trigger level 1 4 characters 10 Trigger level 2 8 characters 11 Trigger level 3 14 characters W 0 5 3 Reserv...

Page 169: ...ables the modem loopback mode and controls the modem output signals Bit Name Description Attribute Reset 31 8 Reserved R 0 7 CTSEN CTS enable bit 0 Disable Auto CTS flow control 1 Enable Auto CTS flow...

Page 170: ...his bit is automatically cleared by HW W 0 8 ABEOIFC End of auto baud interrupt flag clear bit 0 No effect 1 Clear ABEOIF bit This bit is automatically cleared by HW W 0 7 3 Reserved R 0 2 AUTORESTART...

Page 171: ...nd RXEN are set in the same instruction if needed in order to minimize the setup and the hold time of the receiver Bit Name Description Attribute Reset 31 8 Reserved R 0 7 TXEN When this bit is 1 data...

Page 172: ...bit 0 Disable 1 Enable R W 0 14 11 17 USART n Smart card Interface Control register USARTn_SCICTRL n 0 1 Address Offset 0x38 Bit Name Description Attribute Reset 31 24 Reserved R 0 23 16 TC 7 0 Count...

Page 173: ...t AAD enable bit 0 Disable 1 Enable R W 0 1 RXEN RS 485 EIA 485 Receiver enable bit Only work when NMMEN 1 0 Disable 1 Enable R W 0 0 NMMEN RS 485 EIA 485 Normal Multidrop Mode NMM enable bit 0 Disabl...

Page 174: ...ect the USART generates or receives a bit clock on the SCLK pin and applies it to transmit and receive shift registers Synchronous mode should not be used with smart card mode Bit Name Description Att...

Page 175: ...ed I2S and MSB justified data format supported 8 word 32 bit FIFO data buffers are provided Generate interrupt requests when buffer levels cross a programmable boundary Controls include reset stop and...

Page 176: ...S CLCOK CONTROL I2S_PCLK HCLK MCLK_I MCLK_ SOURCE MCLKDIV MCLK MCLKO_EN MCLK_O MCLK_SEL BCLKDIV BCLK_O BCLK_I MS BCLK BCLK_O I2S DIV I2S_MCLK 15 4 2 I2S BLOCK DIAGRAM I2S CLOCK CONTROL 8 x 32 bit TX F...

Page 177: ...SB Left justified Data Format Channel Length Data Length msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb Channel length Left Channel length Right Data length I2S msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb...

Page 178: ...rtex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 178 Version 2 0 Channel Length Data Length msb BCLK SD WS lsb msb lsb msb I2S msb BCLK SD WS lsb msb lsb msb Left Justified msb BCLK SD WS lsb msb...

Page 179: ...79 Version 2 0 15 5 2 I2S FIFO OPERAION 15 5 2 1 MONO 8bit N 3 N 2 N 1 N N 7 N 6 N 5 N 4 16bit N 1 N N 3 N 2 24 bit N N 1 32 bit N N 1 15 5 2 2 STEREO 8bit RIGHT 1 LEFT 1 RIGHT LEFT RIGHT 3 LEFT 3 RIG...

Page 180: ...FO threshold level n R W 0x3 15 Reserved R 0 14 12 TXFIFOTH 2 0 TX FIFO Threshold level 0 TX FIFO threshold level 0 1 TX FIFO threshold level 1 n TX FIFO threshold level n R W 0x3 11 10 DL 1 0 Data Le...

Page 181: ...Attribute Reset 31 17 Reserved R 0 16 CLKSEL I2S clock source selection 0 HCLK 1 EHS XTAL R W 0 15 8 BCLKDIV 7 0 BCLK divider 0 BCLK MCLK 2 1 BCLK MCLK 4 2 BCLK MCLK 6 3 BCLK MCLK 8 n BCLK MCLK 2 n 2...

Page 182: ...R 0 7 RXFIFOTHF RX FIFO threshold flag 0 RXFIFOLV RXFIFOTH 1 RXFIFOLV RXFIFOTH R 0 6 TXFIFOTHF TX FIFO threshold flag 0 TXFIFOLV TXFIFOTH 1 TXFIFOLV TXFIFOTH R 1 5 2 Reserved R 0 1 RIGHTCH Current ch...

Page 183: ...interrupt flag 0 No TX FIFO overflow 1 TX FIFO overflow TX FIFO is full and still being written R 0 3 0 Reserved R 0 15 6 6 I2S Interrupt Clear register I2S_IC Address Offset 0x14 Bit Name Descriptio...

Page 184: ...rge pump to adjust LCD power and bias voltage 16 2 FEATURES 1 Support R C type 2 Support up to 128 4 x 32 dots 3 Common 0 3 and Segment 0 31 V3 V2 CL CL are all shared with GPI O pins 4 Support 1 2 bi...

Page 185: ...ATE 16 4 2 LCD BLOCK DIAGRAM 4C Pump VLCD VLCD LCDREF 1 0 1C Pump LCD_PCLK LCDENB LCDTYPE V2 LCD Voltage Multiplexer LCD_CLK V3 VLCD1 CL CL V3 V2 Generator VCP 3 0 R String BIAS LCDBNK V3 V2 COM Outpu...

Page 186: ...4 500Hz 4 125Hz 1 32KHz 128 250Hz 1 2 250Hz 2 125Hz 1 32KHz 128 250Hz 1 4 250Hz 4 62 5Hz 1 ELS XTAL 32768Hz 0 32768Hz 64 512Hz 1 4 512Hz 4 128Hz 1 32768Hz 128 256Hz 1 4 256Hz 4 64Hz 16 5 2 LCD Driver...

Page 187: ...VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD COM0 COM1 COM2 COM3 SEG0 1010b SEG0 0101b...

Page 188: ..._CTRL1 register User can connect additional external resistance between VLCD1 V3 V2 for more driving current 1 3 Bias V3 2 3 VLCD V2 1 3 VLCD 1 2 Bias V3 V2 1 2 VLCD Note The 0 1uF capacitors of VLCD1...

Page 189: ...CD1 HW will assign COM0 3 SEG0 11 V3 V2 CL CL pin as LCD pins instead of GPIO automatically The charge pump voltage VLCD level is controlled by VCP 3 0 bits in LCD_CCTRL1 register In 1 3 bias conditio...

Page 190: ...all be larger than V3 0 3V if VLCD 3 6V 4 Connect a 0 1uF or 0 47uF capacitor between CL and CL pins Users can adjust the capacitor value depend on the LCD panel size 5 The 0 1uF capacitors of VLCD1 V...

Page 191: ...23 LCD Panel VDD V3 CL CL 0 1uF V2 0 1uF 0 1uF LCD Panel SEG2SEL 1 MCU VLCD1 VDD VLCD3 SEG0 11 SEG24 31 LCD Panel VDD V3 CL CL 0 1uF V2 0 1uF 0 1uF 0 1uF LCD Panel MCU VLCD1 VDD VLCD3 SEG0 11 SEG24 31...

Page 192: ...1SEL 1 SEG2SEL 1 MCU VLCD1 VDD VLCD3 SEG0 11 SEG24 31 LCD Panel LCD Panel VDD 1uF V3 CL CL V2 MCU VLCD1 VDD VLCD3 SEG0 31 LCD Panel VDD 1uF V3 CL CL V2 VLCD2 Note 1 Maximal charge pump voltage is 3 4V...

Page 193: ...30 COM2 29 COM1 28 COM0 27 SEG30 SEG22 SEG14 SEG6 COM3 26 COM2 25 COM1 24 COM0 23 SEG29 SEG21 SEG13 SEG5 COM3 22 COM2 21 COM1 20 COM0 19 SEG28 SEG20 SEG12 SEG4 COM3 18 COM2 17 COM1 16 COM0 15 SEG27 S...

Page 194: ...lication circuit or C type LCD application circuit Bit Name Description Attribute Reset 31 30 Reserved R W 0 29 28 DRIVEP 1 0 LCD panel driving ability 00 Strong Larger panel 01 Medium Medium panel 10...

Page 195: ...ved R W 0 28 ITB Used for internal testing and the only value 0 is allowed R W 1 27 3 Reserved R W 0 2 1 REF 1 0 Resistance selection for LCD Bias Voltage division 00 400K 01 200K 10 100K 11 35K R W 0...

Page 196: ...3V 1 86V 1 40V 0010 2 90V 0 96V 1 93V 1 45V 0011 3 00V 1 00V 2 00V 1 50V 0100 3 06V 1 02V 2 04V 1 53V 0101 3 14V 1 05V 2 10V 1 57V 0110 3 20V 1 07V 2 14V 1 61V 0111 3 30V 1 10V 2 20V 1 66V 1000 3 40V...

Page 197: ...Interrupt Status register LCD_RIS Address offset 0x14 Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 1 Reserved R 0 0 FCIF LCD frame interrupt flag 0 Read No interrupt Write Write 0 t...

Page 198: ...COM0 COM3 R W 0 3 0 SEG8 3 0 SEG8 data for COM0 COM3 R W 0 16 9 9 LCD SEG Memory register 2 LCD_SEGM2 Address Offset 0x28 Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 28 SEG23 3 0...

Page 199: ...0 SEG30 data for COM0 COM3 R W 0 23 20 SEG29 3 0 SEG29 data for COM0 COM3 R W 0 19 16 SEG28 3 0 SEG28 data for COM0 COM3 R W 0 15 12 SEG27 3 0 SEG27 data for COM0 COM3 R W 0 11 8 SEG26 3 0 SEG26 data...

Page 200: ...ry cells that can be used for storing both code and data constants and is located at a specific base address in the memory map of chip The high performance Flash memory module in chip has the followin...

Page 201: ...memory space Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data The read interface consists of a read controller on one sid...

Page 202: ...e only after the MCU has been Reboot User ROM CS0 CS1 CS2 CS3 Description WRITER Read O X X X Erase O O O O WRITER will change the CS level to CS0 Program O O O O FW EEPROM emulation Read O O O O Eras...

Page 203: ...sh memory can be erased page by page or completely Mass Erase 17 8 3 1 PAGE ERASE A page of the Flash memory can be erased using the Page Erase feature of the FMC To erase a page the procedure below s...

Page 204: ...0x0000 0000 Bit Name Description Attribute Reset 31 3 Reserved R 0 2 PGERR Programming error flag 0 Read No error Write Clear this flag 1 Set by HW when The address to be programmed contains a value d...

Page 205: ...W to indicate the data to be programmed Bit Name Description Attribute Reset 31 0 DATA 31 0 Data to be programmed R W 0 17 11 5Flash Address register FLASH_ADDR Address offset 0x10 The Flash address t...

Page 206: ...power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be hig...

Page 207: ...PULL UP DOWN RESISTORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins NJTRST Internal pull up SWDIO JTMS Internal pull...

Page 208: ...Kit SN LINK V3 USB cable to provide communications between the SN LINK V3 and PC IDE Tools KEIL RVMDK SONiX 32 bit MCU Starter Kit SN LINK V3 IDE Tools SONiX 32 bit series Embedded ICE Emulator Featu...

Page 209: ...bit MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK V3 also may be used as a programmer to load firmware from PC to MCU for engineering production even...

Page 210: ...as target board not ready The starter kit can be replaced by target board because of integrated SWD debugger circuitry JP23 External Power USB Type B connector S1 VDD power source is from external po...

Page 211: ...R KIT introduction section in the datasheet to avoid VDD VDD1 VDD2 or VDD3 being short with VLCD LCD Disabled R Type Enabled C Type Enabled JP19 Short Short JP20 Short Open JP21 Short Short P1 0 P1 5...

Page 212: ...Sleep Mode System clock 32KHz 1 3 5 7 100 uA Idd4 Deep sleep Mode Vdd 3 3V 1 3 5 5 uA R type LCD ON with 1 3 bias 1 4 duty 35k bias resistor LCD rate ILRC 64 10 15 uA 1C type LCD ON with 1 3 bias 1 4...

Page 213: ...Vdd 3 3V 1 3 bias 35k bias resistor No panel 5 10 uA 1C Type LCD Operation Current I1CLCD Vdd 3 3V 1 3 bias No panel 18 25 uA 4C Type LCD Operation Current I4CLCD Vdd 3 3V 1 3 bias No panel 7 15 uA C...

Page 214: ...n 2 0 20 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for informa...

Page 215: ...ortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 215 Version 2 0 Supply Current V S Operating Temperature Operating Conditions All pins configured as GPIO outputs driven Low and pull up resistor...

Page 216: ...er Connector Flash IC JP3 Pin Assignment Number Name Number Pin Number Pin Number Pin Number Pin Number Pin 1 VDD 20 41 42 67 VDD 16 33 34 55 VDD 13 25 39 VDD 12 23 37 VDD 10 17 24 VDD 2 GND 17 51 69...

Page 217: ...SN32F760 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 217 Version 2 0 2 2 22 2 2 PACKAGE INFORMATION 22 1 LQFP 80 PIN...

Page 218: ...SN32F760 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 218 Version 2 0 22 2 LQFP 64 PIN...

Page 219: ...cro Controller SONiX TECHNOLOGY CO LTD Page 219 Version 2 0 22 3 LQFP 48 PIN SYMBOLS MIN NOR MAX mm A 1 6 A1 0 05 0 15 A2 1 35 1 45 c1 0 09 0 16 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 00 BSC e 0 5 BSC...

Page 220: ...SN32F760 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 220 Version 2 0 22 4 QFN 46 PIN...

Page 221: ...SN32F760 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 221 Version 2 0 22 5 QFN 33 PIN 5x5...

Page 222: ...MCU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 23 2 MARKING INDETIFICATION SYSTEM Title SONiX 32 bit MCU Production ROM Type F Flash m...

Page 223: ...lash memory 769 LQFP 40 85 Green Package SN32F769W Flash memory 769 Wafer 40 85 SN32F769H Flash memory 769 Dice 40 85 SN32F766JG Flash memory 769 QFN 40 85 Green Package SN32F765JG Flash memory 769 QF...

Page 224: ...roller SONiX TECHNOLOGY CO LTD Page 224 Version 2 0 23 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A October B November C December SONiX Internal Use Day 1 01 2 02 9 09...

Page 225: ...hould Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors...

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