SONIX SN32F755, User Manual

Page: 121 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 121
Version 2.0
Bit Name Description Attribute Reset
31:0
MR[31:0]
Timer counter match value
R/W 0
9.7.8 CT32Bn Capture Control register (CT32Bn_CAPCTRL) (n=0,1,2)
Address Offset: 0x28
The Capture Control register is used to control whether the Capture register is loaded with the value in the
Counter/timer when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both
the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges.

Note: HW will switch I/O Configuration directly when CAP0EN =1.
Bit Name Description Attribute Reset
31:4 Reserved R 0
3
CAP0EN
Capture 0 function enable bit
0: Disable
1: Enable.
.
R/W 0
2
CAP0IE
Interrupt on CT32Bn_CAP0 event: a CAP0 load due to a CT32Bn_CAP0
event will generate an interrupt.
0: Disable
1: Enable
R/W 0
1 CAP0FE
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on
CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
0: Disable
1: Enable
R/W 0
0 CAP0RE
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on
CT32Bn_CAP0 will cause CAP0 to be loaded with the contents of TC.
0: Disable
1: Enable
R/W 0
9.7.9 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1,2)
Address Offset: 0x2C
Each Capture register is associated with a device pin and may be loaded with the counter/timer value when a specified
event occurs on that pin. The settings in the Capture Control register determine whether the capture function is
enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both
edges.
Bit Name Description Attribute Reset
31:0 CAP0[31:0] Timer counter capture value R 0
9.7.10 CT32Bn External Match register (CT32Bn_EM) (n=0,1,2)
Address Offset: 0x30
The External Match register provides both control and status of the external match pins CT32Bn_PWMCTRL[3:0].
If the match outputs are configured as PWM output, the function of the external match registers is determined by the
PWM rules .
Bit Name Description Attribute Reset
31:12 Reserved R 0
11:10
EMC3[1:0]
Determines the functionality of CT32Bn_PWM3.
R/W 0