SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 118
Version 2.0
9.7 CT32Bn REGISTERS
Base Address: 0x4000 6000 (CT32B0)
0x4000 8000 (CT32B1)
0x4000 A000 (CT32B2)
9.7.1
CT32Bn Timer Control register (CT32Bn_TMRCTRL) (n=0,1,2)
Address Offset: 0x00
Note: CEN bit shall be set at last!
Bit
Name
Description
Attribute
Reset
31:7
Reserved
R
0
6:4
CM[2:0]
Counting mode selection
000: Edge-aligned Up-counting mode
001: Edge-aligned Down-counting mode
010: Center-aligned mode 1. The match interrupt flag is set during the
down-counting period
100: Center-aligned mode 2. The match interrupt flag is set during the up-
counting period
110: Center-aligned mode 3. The match interrupt flag is set during both
up-counting and down-counting period
Other: Reserved
R/W
000b
3:2
Reserved
R
0
1
CRST
Counter Reset.
0: Disable counter reset.
1: Timer Counter is synchronously reset on the next positive edge of
PCLK. This is cleared by HW when the counter reset operation finishes.
R/W
0
0
CEN
Counter Enable
0: Disable Counter.
1: Enable Timer Counter for counting.
R/W
0
9.7.2
CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1,2)
Address Offset: 0x04
In Edge-aligned up-counting mode (CM[2:0]=000b), unless it is reset before reaching its upper limit, the TC will count
up to the value 0xFFFFFFFF and then wrap back to the value 0x00000000. This event does not cause an interrupt, but
a Match register can be used to detect an overflow if needed.
In Edge-aligned down-counting mode (CM[2:0]=001b) , the TC[31:0] should be reset to the value of CT32Bn_MR3 after
resetting counter (SW set CRST to 1).
Bit
Name
Description
Attribute
Reset
31:0
TC[31:0]
Timer Counter
R/W
0
