SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 43
Version 2.0
LVD reset:
VDD
VSS
System Normal Run
System Stop
LVD Detect Voltage
Power On
Delay Time
Power
System Status
Power is below LVD Detect
Voltage and System Reset.
The LVD (low voltage detector) is built-in SONiX 32-bit MCU to be brown out reset protection. When the VDD drops
and is below LVD detect voltage, the LVD asserts an interrupt signal to the NVIC. This signal can be enabled for
interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, SW can monitor the
signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of
the chip. The LVD detect level is different by each MCU. The LVD voltage level is a point of voltage and not easy to
cover all dead-band range. Using LVD to improve brown out reset is dependent on application requirement and
environment. If the power variation is very deep, violent and trigger the LVD, the LVD can be the protection. If the
power variation can touch the LVD detect level and make system work error, the LVD can’t be the protection and need
to other reset methods. More detail LVD information is in the electrical characteristic section.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset and return to normal mode after reset sequence. This method also can
improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-
band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system r
ate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
3.1.4
EXTERNAL RESET
External reset function is controlled by
External RESET pin control (SYS0_EXRSTCTRL)
which means external reset function is enabled. External reset pin is Schmitt Trigger structure and low level active. The
system is running when reset pin is high level voltage input. The reset pin receives the low voltage and the system is
reset. The external reset operation actives in power on and normal running mode. During system power-up, the
external reset pin must be high level input, or the system keeps in reset status. External reset sequence is as following.
External reset (only external reset pin enable):
System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization:
All system registers is set as initial conditions and system is ready.
