SONIX SN32F755, User Manual

Page: 53 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 53
Version 2.0
7:5 PSEL[2:0]
Post divider value. P= PSEL[2:0]*2
000~010: Reserved
011: P = 6
100: P = 8
101: P = 10
110: P = 12
111: P = 14
R/W 011b
4:0 MSEL[4:0]
Feedback divider value.
M: 3~31
R/W 0x3
To select the appropriate values for M, P, and F, it is recommended to follow these constraints:
1.
10MHz ≤ F
CLKIN
≤ 25MHz
2.
150MHz ≤ F
VCO
≤ 330MHz
3.
2 < M ≤31
4. F = 1, or 2
5. P = 6, 8, 10, 12, or 14
(duty 50% +/- 2.5%)
6. F
CLKOUT
= 20MHz, 30MHz, 40MHz, 50MHz, 24MHz, 36MHz, 48MHz, 32MHz, 22MHz, 24MHz, 50MHz
with jitter < ±500 ps
Fclkout
Fclkin
V V V V
V V V
V V
V
V
V
44MHz 48MHz 16MHz 22MHz
16MHz
12MHz
12MHz 20MHz 30MHz 40MHz
22MHz
24MHz
25MHz
10MHz
10MHz 50MHz 24MHz 25MHz 32MHz 36MHz
3.3.2.1 RECOMMEND FREQUENCY SETTING
F
VCO
= F
CLKIN
/ F * M
F
CLKOUT
= F
VCO
/ P
F
CLKIN
(MHz) FSEL F=2
FEL
MSEL[4:0]=M
F
VCO
(MHz)
=F
CLKIN
/F*M
PSEL[2:0] P= PSEL[2:0]*2 F
CLKOUT
(MHz)
10 0 1 20 200 5 10 20
10 0 1 22 220 5 10 22
10 0 1 18 180 3 6 30
10 0 1 24 240 3 6 40
10 0 1 30 300 3 6 50
12 0 1 16 192 4 8 24
12 0 1 18 216 3 6 36
12 0 1 24 288 3 6 48
12 0 1 25 300 3 6 50
16 0 1 16 256 4 8 32
16 0 1 18 288 3 6 48
20 1 2 30 300 3 6 50
22 0 1 12 264 3 6 44
24 0 1 12 288 3 6 48
25 0 1 12 300 3 6 50
3.3.3 Clock Source Status register (SYS0_CSST)
Address Offset: 0x08
Bit Name Description Attribute Reset