SONIX SN32F755, User Manual

Page: 161 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 161
Version 2.0
bit1 bit3 bit4 bit5 bit6 Start bit7 Parity Stop
URXD
bit0 bit2
“A” (0x41) or “a” (0x61)
START bit in
USARTn_ABCTRL
Start bit
LSB of “A” or “a”
Rate Counter
16 x Baud Rate
16 Cycles
14.9 SMART CARD MODE
The Smart card mode is enabled by setting the USARTEN bit to 1 and MODE[2:0] = 011b in USARTn_CTRL register,
the USART provides bidirectional serial data on the open-drain UTXD pin. No URXD pin is used in this mode. If a clock
source is needed as an oscillator source into the Smart card, a timer match or PWM output can be used in cases when
a higher frequency clock is needed that is not synchronous with the data bit rate.
The USCLK pin may not be adequate for most asynchronous cards since it will output synchronously with the data and
the data bit rate. SW must use timers to implement character and block waiting times instead.
UTXD
VDD
SN32Fxxx R
PU
ISO 7816
Smart Card
DATA
GPIO RST
VDD
R
PU
GPIO/PWM CLK
VDD
R
PU
14.9.1 SMART CARD SETUP PROCEDURE
A T = 0 protocol transfer consists of 8-bits of data, an even parity bit, and two stop bits t that allow for the receiver of
the particular transfer to flag parity errors through the NACK response. Extra guard bits may be added according to
card requirements.
If no NACK is sent, the next byte may be transmitted immediately after the last guard bit. If the NACK is sent, the
transmitter will retry sending the byte until successfully received or until the SCICTRL retry limit has been met.