SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 106
Version 2.0
Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
00: Timer Mode: every rising PCLK edge
01: Counter Mode: TC is incremented on rising edges on the CAP0 input
selected by CIS bits.
10: Counter Mode: TC is incremented on falling edges on the CAP0 input
selected by CIS bits.
11: Counter Mode: TC is incremented on both edges on the CAP0 input
selected by CIS bits.
8.7.6
CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,1,2)
Address Offset: 0x14
Bit
Name
Description
Attribute
Reset
31:12
Reserved
R
0
11
MR3STOP
Stop MR3: TC and PC will stop and CEN bit will be cleared if MR3
matches TC.
0: Disable
1: Enable
R/W
0
10
MR3RST
Enable reset TC when MR3 matches TC.
0: Disable
1: Enable
R/W
0
9
MR3IE
Enable generating an interrupt based on CM[2:0] when MR3 matches the
value in the TC.
0: Disable
1: Enable
R/W
0
8
MR2STOP
Stop MR2: TC and PC will stop and CEN bit will be cleared if MR2
matches TC.
0: Disable
1: Enable
R/W
0
7
MR2RST
Enable reset TC when MR2 matches TC.
0: Disable
1: Enable
R/W
0
6
MR2IE
Enable generating an interrupt based on CM[2:0] when MR2 matches the
value in the TC.
0: Disable
1: Enable
R/W
0
5
MR1STOP
Stop MR1: TC and PC will stop and CEN bit will be cleared if MR1
matches TC.
0: Disable
1: Enable
R/W
0
4
MR1RST
Enable reset TC when MR1 matches TC.
0: Disable
1: Enable
R/W
0
3
MR1IE
Enable generating an interrupt based on CM[2:0] when MR1 matches the
value in the TC.
0: Disable
1: Enable
R/W
0
2
MR0STOP
Stop MR0: TC and PC will stop and CEN bit will be cleared if MR0
matches TC.
0: Disable
1: Enable
R/W
0
1
MR0RST
Enable reset TC when MR0 matches TC.
0: Disable
1: Enable
R/W
0
0
MR0IE
Enable generating an interrupt based on CM[2:0] when MR0 matches the
value in the TC.
0: Disable
1: Enable
R/W
0
