SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 168
Version 2.0
1
OE
Overrun Error flag.
The overrun error condition is set as soon as it occurs. A USARTn_LS
register read clears OE bit. OE=1 when USART RSR has a new character
assembled and the USARTn_RB FIFO is full. In this case, the
USARTn_RB FIFO will not be overwritten and the character in the
USARTn_RS register will be lost.
0: Overrun error status is inactive.
1: Overrun error status is active.
R
0
0
RDR
Receiver Data Ready flag
RDR=1 when the USARTn_RB FIFO holds an unread character and is
cleared when the USARTn_RB FIFO is empty.
0: USARTn_RB FIFO is empty.
1: USARTn_RB FIFO contains valid data.
R
0
14.11.8 USART n FIFO Control register (USARTn_FIFOCTRL) (n=0,1)
Address Offset: 0x08
This register controls the operation of the USART RX and TX FIFOs.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:6
RXTL[1:0]
RX Trigger Level. These two bits determine how many receiver USART
FIFO characters must be written before an interrupt is activated.
00: Trigger level 0 (1 character)
01: Trigger level 1 (4 characters)
10: Trigger level 2 (8 characters)
11: Trigger level 3 (14 characters)
W
0
5:3
Reserved
R
0
2
TXFIFORST
TX FIFO Reset bit.
0: No impact on either of USART FIFOs.
1: Writing a logic 1 to reset the pointer logic in USART TX FIFO. HW shall
clear this bit automatically.
W
0
1
RXFIFORST
RX FIFO Reset bit.
0: No impact on either of USART FIFOs.
1: Writing a logic 1 to reset the pointer logic in USART RX FIFO. HW shall
clear this bit automatically.
W
0
0
FIFOEN
FIFO enable
0: No effect
1: Enable for both USART Rx and TX FIFOs and USARTn_FIFOCTRL
[7:1] access. This bit must be set for proper USART operation.
W
1
14.11.9 USART n Line Control register (USARTn_LC) (n=0,1)
Address Offset: 0x0C
This register determines the format of the data character that is to be transmitted or received.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7
DLAB
Divisor Latch Access bit
0: Disable access to Divisor Latches.
1: Enable access to Divisor Latches.
R/W
0
6
BC
Break Control bit
0: Disable break transmission.
1: Enable break transmission. Output pin USART TXD is forced to logic 0.
R/W
0
