SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 182
Version 2.0
Other: Reserved
16
Reserved
R
0
15:12
TXFIFOLV[3:0]
TX FIFO used level
0000: 0/8 TX FIFO is used (Empty)
0001: 1/8 TX FIFO is used
0010: 2/8 TX FIFO is used
…
…
1000: 8/8 TX FIFO is used (Full)
Other: Reserved
R
0
11
RXFIFOEMPTY
RX FIFO empty flag
0: RX FIFO is not empty.
1: RX FIFO is empty. Data read from RX FIFO will be zero.
R
1
10
TXFIFOEMPTY
TX FIFO empty flag
0: TX FIFO is not empty.
1: TX FIFO is empty.
R
1
9
RXFIFOFULL
RX FIFO full flag
0: RX FIFO is not full.
1: RX FIFO is full.
R
0
8
TXFIFOFULL
TX FIFO full flag
0: TX FIFO is not full.
1: TX FIFO is full. Write operation to TX FIFO will be ignored.
R
0
7
RXFIFOTHF
RX FIFO threshold flag
0: RXFIFOLV
≦
RXFIFOTH
1: RXFIFOLV > RXFIFOTH
R
0
6
TXFIFOTHF
TX FIFO threshold flag
0: TXFIFOLV
≧
TXFIFOTH
1: TXFIFOLV < TXFIFOTH
R
1
5:2
Reserved
R
0
1
RIGHTCH
Current channel status
0: Current channel is Left channel
1: Current channel is Right channel
R
1
0
I2SINT
I2S interrupt flag
0: No I2S interrupt
1: I2S interrupt occurs.
R
0
15.6.4 I2S Interrupt Enable register (I2S_IE)
Address Offset: 0x0C
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7
RXFIFOTHIEN
RX FIFO threshold interrupt enable bit
0: Disable
1: Enable
R/W
0
6
TXFIFOTHIEN
TX FIFO threshold interrupt enable bit
0: Disable
1: Enable
R/W
0
5
RXFIFOUDFIEN
RX FIFO underflow interrupt enable bit
0: Disable
1: Enable
R/W
0
4
TXFIFOOVFIEN
TX FIFO overflow interrupt enable bit
0: Disable
1: Enable
R/W
0
3:0
Reserved
R
0
15.6.5 I2S Raw Interrupt Status register (I2S_RIS)
Address Offset: 0x10
