SONIX SN32F755, User Manual

Page: 171 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 171
Version 2.0
register must
≥ 3.
Bit Name Description Attribute Reset
31:9 Reserved R 0
8 OVER8
Oversampling value
0: Oversampling by 16
1: Oversampling by 8 (Not supported for IrDA mode)
R/W 0
7:4 MULVAL[3:0]
Baud rate pre-scaler multiplier value = MULVAL[3:0] +1
0000: Baud rate pre-scaler multiplier value is 1 for HW
0001: Baud rate pre-scaler multiplier value is 2 for HW
…
…
1111: Baud rate pre-scaler multiplier value is 16 for HW.
R/W 0
3:0 DIVADDVAL[3:0]
Baud rate generation pre-scaler divisor value. If this field is 0, fractional
baud rate generator will not impact the USART baud rate
R/W 0
14.11.15 USART n Control register (USARTn_CTRL) (n=0,1)
Address Offset: 0x30
In addition to HW flow control (Auto-CTS and Auto-RTS mechanisms), this register enables implementation of SW flow
control.
When TXEN = 1, the USART transmitter will keep sending data as long as they are available. As soon as TXEN bit
becomes 0, USART transmission will stop.
It is strongly suggested to let the USART HW implemented auto flow control features take care of limit the scope of
TXEN to SW flow control.

Note: It is advised that TXEN and RXEN are set in the same instruction if needed in order to minimize the
setup and the hold time of the receiver.
Bit Name Description Attribute Reset
31:8 Reserved R 0
7 TXEN
When this bit is 1, data written to the USARTn_TH register is output on
the TXD pin as soon as any preceding data has been sent.
If this bit is cleared to 0 while a character is being sent, the transmission
of that character is completed, but no further characters are sent until this
bit is set again.
In other words, a 0 in this bit blocks the transfer of characters from the
USARTn_TH register or TX FIFO into the transmit shift register. SW can
clear this bit when it detects that the HW-handshaking TX-permit signal
(CTS) has gone false, or with SW handshaking, when it receives an
XOFF character (DC3). SW can set this bit again when it detects that the
TX-permit signal has gone true, or when it receives an XON (DC1)
character.
R/W 1
6
RXEN
0: Disable RX related function
1: Enable RX
R/W 1
5:4 Reserved R 0
3:1 MODE[2:0]
USARTn Mode
000: UART mode. HW will switch GPIO to UTXDn and URXDn.
001: Modem mode. HW will switch GPIO to UTXDn, URXDn,
UDSRn, UCTSn, UDCDn, URIn, UDTRn and URTSn.
010: Reserved
011: Smart Card mode. HW will switch GPIO to UTXDn, and enable
UTXDn pin with open-drain.
100: Synchronous mode. HW will switch GPIO to UTXDn, URXDn , and
USCLK pin.
101:RS-485 mode. HW will switch GPIO to UTXDn, URXDn pin.
R/W 0