SONIX SN32F755, User Manual

Page: 36 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 36
Version 2.0
Bit Name Description Attribute Reset
31:0
CLRENA[31:0]
Interrupt clear-enable bits.
Write

0: No effect
1: Disable interrupt.
Read

0: Interrupt disabled
1: Interrupt enabled.
R/W 0
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR)
Address: 0xE000 E200 (Refer to Cortex-M0 Spec.)
The ISPR forces interrupts into the pending state, and shows the interrupts that are pending.

Note: Writing 1 to the ISPR bit corresponding to
1. an interrupt that is pending has no effect
2. a disabled interrupt sets the state of that interrupt to pending.
Bit Name Description Attribute Reset
31:0 SETPEND[31:0]
Interrupt set-pending bits.
Write

0: No effect
1: Change interrupt state to pending
Read

0: Interrupt is not pending
1: Interrupt is pending
R/W 0
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR)
Address: 0xE000 E280 (Refer to Cortex-M0 Spec.)
The ICPR removes the pending state from interrupts, and shows the interrupts that are pending.

Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
Bit Name Description Attribute Reset
31:0 CLRPEND[31:0]
Interrupt clear-pending bits.
Write

0: No effect
1: Removes pending state of an interrupt
Read

0: Interrupt is not pending
1: Interrupt is pending
R/W 0
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)
Address: 0xE000 E400 + 0x4 * n (Refer to Cortex-M0 Spec.)
The interrupt priority registers provide an 8-bit priority field for each interrupt, and each register holds four priority fields.
This means the number of registers is implementation-defined, and corresponds to the number of implemented
interrupts.
Bit Name Description Attribute Reset
31:24
PRI_(4*n+3)
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[31:30] of each field, bits [29:24] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.
R/W 0
23:16 PRI_(4*n+2)
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This
R/W 0