SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 94
Version 2.0
7.6 ADC REGISTERS
Base Address: 0x4002 6000
7.6.1
ADC Management register (ADC_ADM)
Address Offset: 0x00
Note:
1. When ADC is enabled (ADENB=1) and global channel is enabled (GCHS=1), the ADC shared pins
transfers to ADC purpose and disable GPIO function and disable pull-up/pull-down resistor by HW
automatically, t
he P2.n/AINn’s digital I/O function including pull-up is isolated.
2. When ADC is disabled (ADENB=0) or global channel is disabled (GCHS=0) , the ADC pins returns to
last GPIO status.
3. If P2.0 is used as external reference voltage input pin, users should set P2.0 as input mode without
pull-up.
Bit
Name
Description
Attribute
Reset
31:18
Reserved
R
0
17
TSENB
Temperature sensor enable bit
0: Disable
1: Enable
R/W
0
16:13
Reserved
R
0
12
AVREFHSEL
ADC high reference voltage source select bit
0: Internal VDD. (P2.0 is GPIO or AIN0 pin)
1: Enable external reference voltage from P2.0
R/W
0
11
ADENB
ADC Enable bit
0: Disable
1: Enable
R/W
0
10:8
ADCKS[2:0]
ADC Clock source divider
000: ADC_PCLK / 1
001: ADC_PCLK / 2
010: ADC_PCLK / 4
011: ADC_PCLK / 8
101: ADC_PCLK / 16
110: ADC_PCLK / 32
Other: Reversed
R/W
0
7
ADLEN
ADC resolution control bit.
0: 8-bit ADC.
1:12-bit ADC.
R/W
0
6
ADS
ADC start control bit.
0: ADC converting stops.
1: Start to execute ADC converting. ADS is cleared when the end of
ADC converting automatically.
R/W
0
5
EOC
ADC status bit Indicates ADC processing status immediately and is
cleared when ADS = 1.
0: ADC progressing.
1: End of converting and reset ADS bit.
R/W
0
4
GCHS
ADC global channel select bit.
0: Disable AIN channel
1: Enable AIN channel
R/W
0
3:0
CHS[3:0]
ADC input channels select bit.
0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3
0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7
1000: AIN8 1001: AIN9 1010: AIN10 1011: AIN11
1100: AIN12 1101: AIN13 1110: AIN14 (Temperature Sensor)
Other: Reserved
R/W
0
