SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 158
Version 2.0
(256 x DLM + DLL) x (1 + DIVADDVAL / MULVAL) = 6.51
Since the value of MULVAL and DIVADDVAL should comply with the following conditions:
1. 1
≤ MULVAL ≤ 15
2. 0
≤ DIVADDVAL ≤ 14
3. DIVADDVAL< MULVAL
Thus, the suggested UART settings would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8 (fill in 7 in the
MULVAL bits). The baud rate generated is 115384, and has a relative error of 0.16% from the originally specified
115200.
14.7 MODEM CONTROL (MC)
If Auto-
RTS mode is enabled, the USART‘s receiver FIFO hardware controls the URTS output of the USART. If the
auto-
CTS mode is enabled, the USART‘s transmitter will only start sending if the UCTS pin is low.
14.7.1 AUTO-RTS
The Auto-RTS function is enabled by setting the RTSEN bit. Auto-RTS data flow control originates in the USARTn_RB
module and is linked to the programmed receiver FIFO trigger level. If auto-RTS is enabled, the data-flow is controlled
as follows:
When the receiver FIFO level reaches the programmed trigger level, URTS is deasserted (to a high value). It is
possible that the sending USART sends an additional byte after the trigger level is reached (assuming the sending
USART has another byte to send) because it might not recognize the deassertion of URTS until after it has begun
sending the additional byte. URTS is automatically reasserted (to a low value) once the receiver FIFO has reached the
previous trigger level. The reassertion of URTS signals the sending USART to continue transmitting data.
If Auto-RTS mode is disabled, the RTSEN bit controls the URTS output of the USART. If Auto-RTS mode is enabled,
hardware controls the RTS output, and the actual value of URTS will be copied in the URTS Control bit of the USART.
As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software.
Example: Suppose the USART operating in type 16550 mode has the trigger level in
to 0x2, then, if Auto-RTS is enabled, the USART will deassert the URTS output as soon as the receive FIFO contains 8
bytes. The URTS output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
URTS
Byte N
Start
Stop
Stop
Start Bit 0~7
…
Start Bit 0~7
Stop
...
Read USARTn RX FIFO
USARTn RX FIFO Level
N-1
N
N-1
N-2
M+2
M+1
…
M
…
M-1
…
URXD
