SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 96
Version 2.0
7.6.4
ADC Interrupt Enable register (ADC_IE)
Address offset: 0x0C
This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example,
it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them.
The most recent results are read by the application program whenever they are needed. In this case, an interrupt is not
desirable at the end of each conversion for some A/D channels.
Bit
Name
Description
Attribute
Reset
31:15
Reserved
R
0
14:0
IE[14:0]
These bits allow control over which A/D channels generate interrupts for
conversion completion. When bit x is one, completion of a conversion on
AIN x will generate an interrupt.
R/W
0
7.6.5
ADC Raw Interrupt Status register (ADC_RIS)
Address offset: 0x10
Bit
Name
Description
Attribute
Reset
31:15
Reserved
R
0
14:0
IF[14:0]
ADC raw interrupt flag. (x = 0 to 14).
0: Read
No interrupt on AINx
Write
Write “0” to the corresponding bit will clear the bit and reset the
Interrupt if the corresponding IE bit is set.
1: Interrupt requirements met on AINx ADC conversion.
R/W
0
