SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 125
Version 2.0
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WATCHDOG TIMER (WDT)
10.1 OVERVIEW
The purpose of the Watchdog is to reset the MCU within a reasonable amount of time if it enters an erroneous state.
When enabled, the Watchdog will generate a system reset or interrupt if the user program fails to "feed" (or reload) the
Watchdog within a predetermined amount of time.
The Watchdog consists of a divide by 128 fixed pre-scaler and an 8-bit counter. The clock is fed to the timer via a
pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0x01.
Hence the minimum Watchdog interval is (T
WDT_PCLK
× 128 × 1) and the maximum Watchdog interval is (T
WDT_PCLK
× 128
× 256).
The Watchdog should be used in the following manner:
1.
Select the clock source for the watchdog timer with WDTCLKSEL register.
2.
Set the prescale value for the watchdog clock with WDTPRE
bits in
3.
Set the Watchdog timer constant reload value in
4.
Enable the Watchdog and setup the Watchdog timer operating mode in
5.
The Watchdog should be fed again by writing 0x55AA to
register before the Watchdog counter
underflows to prevent reset or interrupt.
When the watchdog is started by setting the WDTEN in
register, the time constant value is loaded in the
watchdog counter and the counter starts counting down. When the Watchdog is in the reset mode and the counter
underflows, the CPU will be reset, loading the stack pointer and program counter from the vector table as in the case of
external reset. Whenever the value 0x55AA is written in
register, the WDT_TC value is reloaded in the
watchdog counter and the watchdog reset or interrupt is prevented.
The watchdog timer block uses two clocks: HCLK and WDT_PCLK. HCLK is used for the AHB accesses to the
watchdog registers and is derived from the system clock. The WDT_PCLK is used for the watchdog timer counting.
Several clocks can be used as a clock source for WDT_PCLK clock: IHRC, ILRC, ELS X’tal, and HCLK.
The clock to the watchdog register block can be disabled in
AHB Clock Enable register (SYS1_AHBCLKEN)
for power savings.
Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source.
