SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 155
Version 2.0
14.5 EIA-485/RS-485 MODES
The RS-485/EIA-485 feature allows the USART to be configured as an addressable slave receiver. The addressable
slave receiver is one of multiple slaves receivers controlled by a single master.
The USART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters,
the
parity bit is set to ‘0’.
Each USART slave receiver can be assigned a unique address. The slave can be programmed to either manually or
automatically reject data following an address which is not theirs.
In RS-485 mode, PS bits in
register shall be selected as forced 1 stick parity (Address), or forced stick 0
parity (Data) by SW. In addition, the word length shall be 8 bits by setting WLS bits in USARTn_LC register to 11b by
SW.
14.5.1 RS-485/EIA-485 NORMAL MULTIDROP MODE (NMM)
Setting the NMMEN bit in
register enables this mode. In this mode, an address is detected
when a received byte causes the USART to set the parity error and generate an interrupt.
If the receiver is disabled (RXEN = 0 in
register), any received data bytes will be ignored and
will not be stored in the RXFIFO. When an address byte is detected (parity bit =
‘1’) it will be placed into the RXFIFO
and a parity error (PE) Interrupt will be generated. The processor can then read the address byte and decide whether
or not to enable the receiver to accept the following data.
While the receiver is enabled (RXEN = 1 in
register), all received bytes will be accepted and
stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity
error interrupt will be generated and the processor can decide whether or not to disable the receiver.
14.5.2 RS-485/EIA-485 AUTO ADDRESS DETECTION (AAD) MODE
When both NMMEN (9-bit mode enable) bit and AADEN (AAD mode enable) bit in
set, the USART is in auto address detect mode.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the
If the receiver is disabled (RXEN = 0 in
register), any received byte will be discarded if it is
either a data byte or an address byte which is different from the value in
When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the
receiver will be automatically enabled (RXEN bit will be set by HW). The receiver will also generate an RX Data
Available (RDA) Interrupt.
While the receiver is enabled (RXEN = 1 in
register), all bytes received will be accepted and
stored in the RXFIFO until an address byte which is different from the MATCH value is received. When this occurs, the
receiver will be automatically disabled by HW (RXEN bit will be cleared by HW), the received non-matching address
character will not be stored in the RXFIFO.
14.5.3 RS-485/EIA-485 AUTO DIRECTION CONTROL (ADC)
RS485/EIA-485 mode includes the option of allowing the transmitter to automatically control the state of the DIR pin as
a direction control output signal. Set ADCEN bit in
register to enable this feature.
The ADCEN bit takes precedence over all other mechanisms controlling the direction control pin with the exception of
loopback mode.
