SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 115
Version 2.0
9.6 PWM
9.6.1
PWM Mode 1
PWMn is 0 when TC<MRn during Up-counting period
PWMn is 0 when TC≤MRn during Down-counting period
Take Edge-aligned Up-counting Mode as example,
1.
All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero)
unless their match value in CT32Bn_MR0~3 registers is equal to zero.
2.
Each PWM output will go HIGH when its match value is reached. If no match occurs, the PWM output remains
continuously LOW.
3.
If a match value larger than the PWM cycle length is written to the CT32Bn_MR0~3 registers, and the PWM
signal is HIGH already, then the PWM signal will be cleared on the next start of the next PWM cycle.
4.
If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM
output will be reset to LOW on the next clock tick. Therefore, the PWM output will always consist of a one clock
tick wide positive pulse with a period determined by the PWM cycle length.
5.
If a match register is set to zero, then the PWM output will go to HIGH the first time the timer goes back to zero
and will stay HIGH continuously.
CT32Bn_MR0=60
0
100 (TC resets)
60
25
CT32Bn_MR1=25
PWM0
PWM1
CT32Bn_MR2=100
PWM2
CT32Bn_TC
Note:
When the match outputs are selected to perform as PWM outputs, the timer reset (MRnRST) and
register must be set to zero except for the match
register setting the PWM cycle length. For this register, set the MRnR bit to one to enable the timer
reset when the timer value matches the value of the corresponding match register.
The following figure shows the PWM mode 1 wave form in Center-aligned counting mode.
Case 1: The
to 7, the
