SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 213
Version 2.0
*ADC current consumption
I
ADC
Vdd=3.3V, ADS=0
-
220
-
uA
ADC Clock Frequency
F
ADCLK
Vdd=3.3V
-
-
16
MHz
ADC Conversion Cycle Time
F
ADCYL
VDD=2.5V~5.5V
64
-
-
1/F
ADCLK
ADC Sampling Rate
F
ADSMP
Vdd=3.3V
-
-
250
KHz
Differential Nonlinearity
DNL Vdd=5.5V , AVREFH=2.4V
-1
-
+1
LSB
Integral Nonlinearity
INL Vdd=5.5V , AVREFH=2.4V
-1
-
+1
LSB
No Missing Code
NMC Vdd=5.5V , AVREFH=2.4V
10
-
12
Bits
ADC offset Voltage
V
ADCoffset
-5
-
+5
mV
Temperature sensor Range
TR
Temperature Sensor Operation Range
-10
-
+70
℃
Temperature Sensitivity
TS
Temperature Sensor Sensitivity.
-
3.53
-
mV/
℃
Temperature Sensor Accuracy
ETS
One Temperature point Calibration.
-10
-
+10
%
Two Temperature points Calibration.
-1
-
+1
%
FLASH
Supply Voltage
Vdd1
1.8
-
Vdd
V
Endurance time
T
EN
Erase + Program
20K
*100K
-
Cycle
Page erase time
T
PE
1-Page (1024 bytes).
-
25
30
ms
1-Word Programming time
T
PG
1-Word (32 bits).
-
60
70
us
LCD Driver
R-Type LCD Operation Current
I
RLCD
Vdd = 3.3V, 1/3 bias, 400k,bias resistor, No panel
-
3
5
uA
Vdd = 3.3V, 1/3 bias, 35k,bias resistor, No panel
-
5
10
uA
1C-Type LCD Operation Current
I
1CLCD
Vdd = 3.3V, 1/3 bias, No panel
-
18
25
uA
4C-Type LCD Operation Current
I
4CLCD
Vdd = 3.3V, 1/3 bias, No panel
-
7
15
uA
C-Type VLCD Output Voltage
V
LCD1
Vdd = 1.8~5.5V. VCP[3:0] = 0011b
2.85
3.0
3.15
V
MISC
Low Voltage Detector
LVD
Interrupt/Reset
Level 0
1.80
V
Level 1
2.00
V
Level 2
2.40
V
Level 3
2.70
V
Level 4
3.00
V
Level 5
3.60
V
IHRC Freq.
F
IHRC
T=25
℃
,
Vdd=1.8V~ 5.5V
11.88
12
12.12
MHz
T=-40
℃
~85
℃
,
Vdd=1.8V~5.5V
11.70
12
12.30
MHz
* These parameters are for design reference, not tested.
[1] I
DD
measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled and VDD=3.3V
[2] IHRC and ILRC are enabled
, external X’tal is disabled, and PLL is disabled.
[3] LVD and all peripherals are disabled.
[4] IHRC is disabled, external
high X’tal is enabled, and PLL is enabled.
[5] All oscillators and analog blocks are turned off.
[6] DPDWAKEUP pin is pulled HIGH internally.
[7] ILRC is enabled, IHRC and external X’tal are disabled, and PLL is disabled.
[8] VDD is the Vddio of P0.8~P0.9, P2.0~P2.15, and P3.10~P3.15; VDD1 is the Vddio of P1.6~P1.15, and P3.0~P3.9; VDD2 is the Vddio of
P1.0~P1.5, and P0.10~P0.15; VDD3 is the Vddio of P0.0~P0.7.
