SONIX SN32F755, User Manual

Page: 91 / 225

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 91
Version 2.0
2. ADC_PCLK shall be less than 16MHz.
3. The analog input level must be between the AVREFH and AVREFL.
4. The AVREFH level must be between the AVDD and 2.0V.
5. ADC programming notice

Disable ADC
(set ADENB = “0”) before enter low-power (Sleep/Deep-sleep/Deep power-
power-down) mode to save power consumption.
 Delay 100us after enable ADC (set ADENB = “1”) to wait ADC circuit ready for conversion.
7.2 ADC CONVERTING TIME
The ADC converting time is from ADS=1 (Start to ADC convert) to EOC=1 (End of ADC convert). The converting time
duration is depend on ADC resolution and ADC clock rate.
ADC clock source is controlled by ADCKS[2:0] bits. The ADC converting time affects ADC performance. If input high
rate analog signal, it is necessary to select a high ADC converting rate. If the ADC converting time is slower than
analog signal variation rate, the ADC result would be error. So to select a correct ADC clock rate and ADC resolution to
decide a right ADC converting rate is very important.
12-bit ADC conversion time = 1/(ADC clock /4)*16 sec
ADLEN ADCKS
[2:0]
ADC Clock
ADC_PCLK = 4 MHz ADC_PCLK = 16 MHz
ADC
Conversion
Time (us)
ADC
Conversion
Rate (KHz)
ADC
Conversion
Time (us)
ADC
Conversion
Rate (KHz)
1
000 ADC_PCLK 16 62.5 4 250
001 ADC_PCLK/2 32 31.25 8 125
010 ADC_PCLK/4 64 15.625 16 62.5
011 ADC_PCLK/8 128 7.813 32 31.25
100 ADC_PCLK/16 256 3.906 64 15.625
101 ADC_PCLK/32 512 1.953 128 7.813
8-bit ADC conversion time = 1/(ADC clock /4)*12 sec
ADLEN ADCKS
[2:0]
ADC Clock
ADC_PCLK = 4 MHz ADC_PCLK = 16 MHz
ADC
Conversion
Time (us)
ADC
Conversion
Rate (KHz)
ADC
Conversion
Time (us)
ADC
Conversion
Rate (KHz)
0
000 ADC_PCLK 12 83.333 3 333.333
001 ADC_PCLK/2 24 41.667 6 166.667
010 ADC_PCLK/4 48 20.83 12 83.333
011 ADC_PCLK/8 96 10.416 24 41.667
100 ADC_PCLK/16 192 5.208 48 20.83
101 ADC_PCLK/32 384 2.604 96 10.416