SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 143
Version 2.0
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I2C
13.1 OVERVIEW
The I2C bus is bidirectional for inter-IC control using only two wires: Serial Clock Line (SCL) and Serial Data line (SDA).
Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver)
or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is
only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. It is
also SMBus 2.0 compatible.
Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C bus:
Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver.
The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next
follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all
received bytes other tha
n the last byte. At the end of the last received byte, a “not acknowledge” is returned. The
master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated START condition is also the
beginning of the next serial transfer, the I2C bus will not be released.
The I2C interface is byte oriented and has four operating modes:
Master transmitter mode
Master receiver mode
Slave transmitter mode
Slave receiver mode
13.2 FEATURES
The I2C interface complies with the entire I2C specification, supporting the ability to turn power off to the ARM
Cortex-M0 without interfering with other devices on the same I2C-bus.
Standard I2C-compliant bus interfaces may be configured as Master or Slave.
I2C Master features:
Clock generation
Start and Stop generation
I2C Slave features:
Programmable I2C Address detection
Optional recognition of up to four distinct slave addresses
Stop bit detection
Supports different communication speeds:
Standard Speed (up to 100KHz)
Fast Speed (up to 400 KHz)
Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the
bus.
Programmable clock allows adjustment of I2C transfer rates.
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
