SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 170
Version 2.0
14.11.12
USART n Scratch Pad register (USARTn_SP) (n=0,1)
Address Offset: 0x1C
This
register has no effect on the USART operation. This register can be written and/or read at user’s discretion. There
is no provision in the interrupt interface that would indicate to the host that a read or write of this register has occurred.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
PAD[7:0]
A readable, writable byte.
R/W
0
14.11.13
USART n Auto-baud Control register (USARTn_ABCTRL) (n=0,1)
Address Offset: 0x20
This register controls the process of measuring the incoming clock/data rate for the baud rate generation and can be
read and written at user’s discretion. Besides, it also controls the clock pre-scaler for the baud rate generation. The
reset value of the register keeps the fractional capabilities of USART disabled making sure that USART is fully SW and
HW compatible with USARTs not equipped with this feature.
Bit
Name
Description
Attribute
Reset
31:10
Reserved
R
0
9
ABTOIFC
Auto-baud time-out interrupt flag clear bit
0: No effect
1: Clear ABTOIF bit. This bit is automatically cleared by HW.
W
0
8
ABEOIFC
End of auto-baud interrupt flag clear bit
0: No effect.
1: Clear ABEOIF bit. This bit is automatically cleared by HW.
W
0
7:3
Reserved
R
0
2
AUTORESTART
Restart mode
0: No restart
1: Restart in case of timeout (counter restarts at next USART RX falling
edge)
R/W
0
1
MODE
Auto-baud mode select bit.
0: Mode 0.
1: Mode 1.
R/W
0
0
START
This bit is automatically cleared after auto-baud completion.
0: Auto-baud stop (auto-baud is not running).
1: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared by HW after auto-baud completion.
R/W
0
14.11.14
USART n Fractional Divider register (USARTn_FD) (n=0,1)
Address Offset: 0x28
This register
controls the clock prescaler for the baud rate generation and can be read and written at the user’s
discretion. This prescaler takes the APB clock and generates an output clock according to the specified fractional
requirements.
In most applications, the USART samples received data 16 times in each nominal bit time, and sends bits that are 16
input clocks wide. OVER8 bit allows software to control the ratio between the input clock and bit clock. This is required
for smart card mode, and provides an alternative to fractional division for other modes.
Note: If the fractional divider is active (DIVADDVAL>0) and USARTn_DLM=0, the value of the
USARTn_DLL
