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17-2. Bank Base Address
The ROM disk area to be accessed is determined by inputting ad-
dress signals from the ISA bus.
The ROM disk area is base a (0000h-3FFFh) with the size of
16KB.
17-3. Bank Switch
For ROM bank 512 to 895, chip select and bank switch are performed
by issuing address signal BA0-6 and chip select signal FROS#0-2
from the PSC2.
18. PS RAM Disk
18-1. Outline
Toshiba’s TC51V8512AF-12
3V single power source
512K words
×
8 bits
32-pin TSOP 4M bits pseudo static RAM
Relocatable bank base address: C0000h,
C8000h,
D0000h,
D8000h, E0000h, and E8000h
Bank switch of 16KB block: Bank 0 to 191
Refresh: 2048 cycles/32ms (15.625us)
18-2. Bank Base Address
The RAM disk area to be accessed is determined by inputting ad-
dress signals from the ISA bus.
The RAM disk area is base a (4000h-7FFFh) with the size of
16KB.
18-3. Bank Switch
Chip select and bank switch are performed by issuing address signal
BA0-5 and chip select signal PRAS#0-2 from the PSC2.
19. Analog Touch Panel
19-1. Outline
The analog touch panel is controlled by Fujitsu’s control IC N010-
0559-V021, and the CPU issues commands to this panel through
serial interface.
Light load input type
Communication mode: Full duplex communication mode, serial inter-
face
Transmission rate: 9600 bps
Data transmission method: asynchronous start-stop synchronization
Signal level: TTL level
Data format: Binary
Bit form: Start bit (1) + data bit (8) + stop bit (1), non-parity
Interface signal: RXD/TXD
Sampling speed: 100pps maximum
20. Reset circuit
20-1. Block diagram
The RESETDRV in the PSC2 resets the ISA device in the PSC2.
The PHOLD is a control signal turning ON/OFF of AC input by the
software. The PHSNS is a sense signal.
20-2. Timing Chart
(A) Power cut:
SSR1 07F1h[1]=0 is set.
(B) Power off:
SSR1 07F1h[1]=0 is set.
Power supply is assured only for 50ms from the falling of ACL, setting
SSR1 07F1h[1]=0 must be performed within 50ms from the falling of
ACL. When this operation is not performed and the power supply is
active, the PSC2 sets SSR1 07F1h[1]=0 at 200ms after the falling of
ACL.
20-3. Control of Power ON/OFF and Register
Sensing State of AC SW
General purpose port (PSC+408h)=588h
HIOP
b7 b6
b5
b4
b3 b2
b1
b0
Read
0
0
PHOLD
SLEEP
0
0
PHSNS
MLOCK
Write
0
0
PHOLD
SLEEP
0
0
0
0
Bit 7-6:
Not used.
Bit 5:
AC power supply hold signal
PHOLD="0": Power is turned off when the AC switch is set
OFF.
PHOLD="1": Power continues to be supplied even when
the AC switch is set OFF.
The initial value of PHOLD is "0". To prohibit power off by
the manual operation of the AC switch, set PHOLD to "1".
When not prohibiting power off by the manual operation of
the AC switch, set PHOLD to "0".
PWRGD
Q
S
D
Q
CK
R
SDEN
7F1h
200ms
300ms
POFF#
PWRGOOD
P/S unit
5V
Voltage
Detector
PHSN
PHOL
ACL
PSC2
PWRGOOD
POFF#
PWRGD
RESETDRV
RSTDR RSTDRV#
PWRGD
PWRGD
RESET#
FireStar
RESET
CPURST
Pentium
PWGOOD
ACL
(200ms)
SDEN
300ms
RESET#
RSTDR
300ms
(A)
(A)
200ms
5 – 38
Summary of Contents for UP-5300
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Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
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