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Symbol
Type
Name and Function
PRDY
O
The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin
going active or Probe Mode being entered.
PWT
O
The page write-through pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry.
The PWT pin is used to provide and extemal writeback indication on a page-by-page basis.
R/S#
I
The run/stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and
place it into an idle state. A high to low transition on the R/S# pin will interrupt the processor and cause it to stop
execution at the next instruction boundary.
RESET
I
RESET forces the processor to begin execution at a known state. All the processor internal caches will by invalidated
upon the RESET. Modified lines in the data cache are not written back. FLUSH# and INIT are sampled when RESET
transitions from high to low to determine if tristate test mode will be entered or if BIST will be run.
SCYC
O
The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be
locked together. This signal is defined for locked cycles only. It is undefined for cycles which are locked.
SMI#
I
The system management interrupt causes a system management interrupt request to be latched internally. When the
latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode.
SMIACT#
O
An active system management interrupt active output indicates that the processor is operating in System Management
Mode.
STPCLK#
I
Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor with voltage
reduction technology thereby causing the core to consume less power. When the CPU recognizes STPCLK#, the
processor will stop execution ont eh next instruction boundary, unless superseded by a higher priority interrupt, and
generate a Stop Grant Acknowledge cycle. When STPCLK# is asserted, the processor will still respond to extemal
snoop requests.
TCK
I
The testability clock input provides the clocking function for the processor boundary scan in accordance with the IEEE
Boundary Scan interface (Standard 1149.1). It is used to clock state information and data into and out of the processor
during boundary scan.
TDI
I
The test data input is a serial input for the test logic. TAP instructions and data are shifted into the processor on the
TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state.
TDO
O
The test data output is a serial output of the test logic. TAP instructions and data are shifted out of the processor on the
TDO pin on TCK’s falling edge when the TAP controller is in an appropriate state.
TMS
I
The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP
controller state changes.
TRST#
I
When asserted, the test reset input allows the TAP controller to be asynchronously initialized.
Vcc2
I
These pins are the 2.9V (3.1V for 150 MHz) power inputs to the Pentium processor with voltage reduction technology.
Vcc3
I
These pins are 3.3V power inputs to the Pentium processor with voltage reduction technology.
Vss
I
These pins are the ground inputs to the Pentium processor with voltage reduction technology.
W/R#
O
Write/read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is
asserted. W/R# distinguishes between write and read cycles.
WB/WT#
I
The writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line
basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
8. Chipset
8-1. Introduction
OPTi’s FireStar Plus (82C700U3.2) is used.
FireSter Strap Options
Pin No.
Pin Name
Internally at Reset
Setting
Function
N25
RTCRD#
Pull low
Pull high (Vcc5)
PCICLK1 Enable
N26
RTCWR#
Pull low
Pull low
PCICLK2 Disable
J24
ROMCS#
Pull low
Pull low
PCICLK3-5 Disable
J26
KBDCS#
Pull low
Pull low
AF5
INTR
Pull high
Pull high
PCIVCC = 3.3V
AD5
NMI
Pull high
Pull high
DRAMVCC = 3.3V
AC6
IGERR#
Pull low
Pull low
ISAVCC = 5.0V
H24
DBEW#
Pull low
Pull low
PPWR = Normal mode
R5
BOFF#
Pull low
Pull low
PPWR0# Selected
N24
RTCAS
Pull high
Pull low
Normal decode ISA mode
R3
A20M#
Pull high
Pull high (Vcc3)
AB14
PCICLK0
Pull low
Pull low
No MCACHE support
B7
RSVD
Pull low
Pull low
CPUVCC = 3.3V
The internal resister is about 50 kohm.
The external resister is 10 kohm.
5 – 10
Summary of Contents for UP-5300
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Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
Page 108: ...6 I N V E R T E R P W B A S i d e B S i d e 7 L C D R E L A Y P W B A S i d e B S i d e 9 7 ...