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Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
PIO14
AC20
I/O
(4mA)
PCIDV1
8Eh
≠
00h
Programmable Input/Output 14: See Section 3.3, "Programmable
I/O Pins", on page 33 for more details.
CMD#
AB20
O
(4mA)
SYSCFG
16h[7, 5]
Command: Dedicated CISA output used to signal a data transfer
command.
DIRTY
I/O
(4mA)
Tag Dirty Bit: This dirty bit allows the tag data to be 8 bit wide
instead of 7.
ATCLK
AA22
O
(8mA)
ISA Bus Clock: This signal is derived from an internal division of
PCICLK. It is used to sample and drive all ISA synchronous signals.
PCIDV1 47h[5:4] sets the ATCLK:
00 = 4
10 = 2
01 = 3
11 = PCICLK
The ATCLK is also used to demultiplex and sample externally
multiplexed inputs. During Suspend, it is possible to output 32KHz on
this pin, or drive it low.
IOCHRDY
AB26
I/O
(8mA)
I/O Channel Ready: Resources on the ISA bus deassert IOCHRDY
to indicate that wait states are required IOCHRDY to indicate that
wait states are required to complete the cycle. IOCHRDY is an input
when FireStar owns the ISA bus and is an output when an external
ISA bus master owns the ISA bus. IOCHRDY is automatically
tristated in Suspend.
BALE
W22
O
(8mA)
Bus Address Latch Enable: BALE is an active high signal asserted
to indicate that the address, AEN, and SBHE# signal lines are valid.
BALE remains asserted throughout ISA master and DMA cycles.
ISA Bus Interface
MRD#
AC26
I/O
(8mA)
Memory Read: MRD# is the command to a memory slave that it may
drive data onto the ISA data bus. MRD# is an output when FireStar is
a master on the ISA bus. MRD# is an input when an ISA master,
other than FireStar, owns the ISA bus.
MWR#
AB23
I/O
(8mA)
Memory Write: MWR# is the command to a memory slave that it
may latch data from the ISA data bus. MWR# is an output when the
FireStar owns the ISA bus. MWR# is an input when an ISA master,
other than FireStar, owns the ISA bus.
IOR#
AB24
I/O
(8mA)
I/O Read: IOR# is the command to an ISA I/O slave device that the
slave may drive data on to the ISA data bus (SD[15:0]). The I/O slave
device must hold the data valid until after IOR# is negated. IOR# is
an output when FireStar owns the ISA bus. ISA# is an input when an
external ISA master owns the ISA bus.
IOW#
AB25
I/O
(8mA)
I/O Write: IOW# is the command to an ISA I/O slave device that the
slave may drive latch data from the ISA data bus (SD[15:0]). IOR# is
an output when FireStar owns the ISA bus. IOW# is an input when an
external ISA master owns the ISA bus.
SMRD#
W26
I/O
(8mA)
PCIDV1
95h = 00h
System Memory Read: FireStar asserts SMRD# to request a
memory slave to provide data. If the access is below the 1MB range
(00000000h-000FFFFFh) during DMA compatible, IPC master, or
ISA master cycles, FireStar asserts SMRD.
SMWR#
V22
I/O
(8mA)
PCIDV1
96h = 00h
System Memory Write: FireStar asserts SMWR# to request a
memory slave to accept data from the data lines. If the access is
below the 1MB range (00000000h-000FFFFFh) during DMA
compatible, IPC master, or ISA master cycles, FireStar asserts
SMWR#.
AEN
M22
I/O
PCIDV1
C2h [1] = 0
Address Enable: AEN is asserted during DMA cycles to prevent I/O
slaves from misinterpreting DMA cycles as valid I/O cycles. When
asserted, AEN indicates to an I/O resource on the ISA bus that a
DMA transfer is occurring. This signal is asserted also during refresh
cycles. AEN is driven low upon reset.
IO16#
W23
I/O
PCIDV1
92h = 00h
16-Bit I/O Chip Select: This signal is driven by I/O devices on the
ISA bus to indicate that they support 16-bit I/O bus cycles.
M16#
W24
I/O
PCIDV1
93h = 00h
16-Bit Memory Chip Select: ISA slaves that are 16-bit memory
devices drive this signal low. MEMCS16# is an input when FireStar
owns the ISA bus. FireStar drives this signal low during ISA master to
PCI memory cycles.
5 – 19
Summary of Contents for UP-5300
Page 103: ... B S i d e 9 2 ...
Page 105: ... B S i d e 9 4 ...
Page 106: ...3 V G A P W B A S i d e B S i d e 9 5 ...
Page 107: ...4 R i s e r P W B A S i d e B S i d e 5 T P S w i t c h P W B S w i t c h P W B 9 6 ...
Page 108: ...6 I N V E R T E R P W B A S i d e B S i d e 7 L C D R E L A Y P W B A S i d e B S i d e 9 7 ...