Sharp UP-5300, Service Manual

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10-3. Pin description
10-3-1. PCI bus-related pins
Pin name I/O Level Function
CLK I 5VTTL PCI Clock
PCI bus synchronization clock. Possible to input up to 33MHz.
AD[31:0] I/O 5VTTL Address Data Bus
Time shared PCI bus address or data bus
C/BE[3:0]# I 5VTTL Command/Byte Enable
In the address phase, it represents memory access, I/O access, configuration access and read/write
command.
In the data phase, it functions as the byte enable signal.
PAR I/O 5VTTL Bus Parity
Parity input, and parity output for the read command
FRAME# I 5VTTL Cycle Frame
The period during which data is transferred. The transfer cycle starts when input is low and is terminated by
the next transfer data of high input.
IRDY# I 5VTTL Initiator Ready
One data phase ends in a cycle where both IRDY# and TRDY# are LOW simultaneously.
TRDY# O Target Ready
One data phase ends in a cycle where both IRDY# and TRDY# are LOW simultaneously.
STOP# O Stop
This signal is output when this LSI aborts the data transfer being currently executed.
IDSEL I 5VTTL Initialization Device Select
The chip select signal of configuration register. The configuration register can be accessed when this signal
is high.
It is recommended to connect the AD24 to AD31 when the AD signal is used as IDSEL.
DEVSEL# O Device Select
LOW is output when the request for accessing the LSI is detected.
BIOSCS# O BIOS Chip Select
LOW is output when access to VIDEO BIOS is accepted.
10-3-2. Memory access-related pins
Pin name I/O Level Function
MA[9:0] I/O CMOS Memory Address
Address for display memory
It becomes input mode when resetting. MA[2:0] determines the host type of the chip.
MA[9:3] is taken into the internal latch as data about the expansion terminal monitor register.
RAS# O RAS Address Strobe
This output is the strobe signal for low address latch.
CASO# O Lower CAS Address Strobe for RAMO
This output is the strobe signal for RAMO’s lower byte column address.
CAS1# O Upper CAS Address Strobe for RAMO
This output is the strobe signal for RAMO’s upper byte column address.
CAS2# O Lower CAS Address Strobe for RAM1
This output is the strobe signal for RAM1’s lower byte column address.
CAS3# O Lower CAS Address Strobe for RAM1
This output is the strobe signal for RAM1’s upper byte column address.
WE# O Write Enable
This output is the data write signal.
MD[31:0] I/O CMOS Memory Data bus
This is DRAM memory data. Can be switched to the 16-bit bus by changing the register setting.
This data bus is also used for reading the video BIOS through PCI bus connection.
MD[15:0] and MD[23:16] correspond to the BIOS ROM address and BIOS ROM data input, respectively.
10-3-3. LCD-related pins
Pin name I/O Level Function
BACKON I/O CMOS Back Light On
This output is the signal which requests lighting of the back light.
LOW: Off
HIGH: On
This terminal can also be used as a general-purpose I/O port.
In the external RAMDAC mode, this terminal outputs the register WR signal to RAMDAC.
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